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- Dr. Neeraj Kumar Misra is Associate Professor at Vellore Institute of Technology (VIT) -AP University Amaravati, Indi... moreDr. Neeraj Kumar Misra is Associate Professor at Vellore Institute of Technology (VIT) -AP University Amaravati, India. He has the Senior Member of IEEE. He was awarded Full-time Ph.D. degree under TEQIP-II. He did PGD in Machine Learning & Artificial Intelligence from NIT Warangal. His research interests include Reversible and Quantum computing and QCA. He has published more than 50 papers (22 from thesis) in Springer, Elsevier, IEEE, Taylor & Francis, World Scientific, and Inderscience etc, 03 Books, 11 Book Chapter in Springer. He has a member of IEEE (92318696), ISTE (LM 125080).edit
- Associate Professoredit
In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and... more
In nano communication, fault-tolerant networks play a crucial role in error control. A significant practical challenge for nanocircuits is their ability to transmit information over networks to different endpoints. Fault-tolerant and reversible circuits have control error problems. The advantage of a quantum gate-based architecture is that it prevents heat loss, and it has been extensively researched. In this article, we have developed reversible multiplexers (mux's), half-adder (HA), and full-adder (FA) and latches that are fault-tolerant by making use of new gate and implementing them on the IBM Qiskit platform. A power-efficient and fault-tolerant mux's and latches is proposed that uses reversible gates to preserve parity. Multiplexer kinds such as 2:1, 4:1, and n:1 is covered in depth by the new Parity Preserving Multiplexer (PPM) gate and verified by IBM-Qiskit. An algorithmic design for an n:1 multiplexer is invented. In order to assess a PPM gate effectiveness, 13 standard Boolean functions and 8 standard types of gates are implemented. The PPM quantum gate is built using quantum assembly code (QAC), which runs on IBM Quantum Lab and IBM Quantum Composer platforms to measure the output qubits. Additional HA, muxes, and latches design led to the code creation in the Qiskit platform, which was used to measure the output qubits. A comparison of the D-latch, T-latch, JK-latch, and mux designs with existing circuits shows a reduction in quantum cost (qc) and junk output (go) and the implementation of a custom design in the IBM-Qiskit platform to measure output qubits is a first time in literature.
Research Interests:
Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of... more
Quantum-dot cellular automata (QCA) has recently attracted significant notice thanks to their inherent ability to decrease energy dissipation and decreasing area, which is the primary need of digital circuits. However, the lack of resistance of QCA circuits under defects in previous works is a vital challenge affecting the stability of the circuit and output production. In addition, with the high defect rate in QCA, suggesting resistance and stable structures is critical. Furthermore, the 3-input majority gate is a fundamental component of QCA circuits; therefore, improving this essential gate would enable the development of fault-tolerant circuits. This paper recommends a 3-input majority gate which is 100% fault-tolerant against single-cell omission defects. Moreover, the fundamental gates are introduced based on the proposed gate. In addition, an adder and a 1:2 decoder are also designed. Using QCADesigner 2.0.3 and QCAPro software, simulations of structures and analysis of power consumption are performed.
Research Interests:
Over the past several decades, the goal of Very Large-Scale Integration (VLSI) has been to miniaturize chip size while increasing computing speed and lowering power consumption. At this time, miniaturisation of size, high computing speed,... more
Over the past several decades, the goal of Very Large-Scale Integration (VLSI) has been to miniaturize chip size while increasing computing speed and lowering power consumption. At this time, miniaturisation of size, high computing speed, and low power consumption do not appear to be capable of meeting consumer demand due to limitation in transistor geometry. Quantum dot Cellular Automata (QCA) is a more promising methodology with the potential to optimize power, speed, and area on a nano scale. Combinational circuit design has received a signi cant amount of research and development attention in the eld of nano-computing. This article proposed design of a decoder with an accurate clocking mechanism in QCA and the best design. In terms of cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost, the novel 2-to-4 decoder achieves values of 87, 0.10 m 2 , 0.0281 m 2 , 28.1, 2.5, 0.625, and 0.25, which is better than the prior work. In comparison to a standard design, the improvements in cell count, total area, cell area, area coverage, latency, QCA cost, and quantum cost are 72.
Research Interests:
A supercapacitor is a type of electrical component that has larger capacitance, due to asymmetric behavior with better power density, and lower ESR (effective series resistance) than conventional energy-storage components. Supercapacitors... more
A supercapacitor is a type of electrical component that has larger capacitance, due to asymmetric behavior with better power density, and lower ESR (effective series resistance) than conventional energy-storage components. Supercapacitors can be used with battery technology to create an effective energy storage system due to their qualities and precise characterization. Studies have shown that the use of quantum dots as electrodes in supercapacitors can significantly increase their effectiveness. In this research article, we have used a Drude model based on free electrons (asymmetric nature) to describe the supercapacitor's discharging characteristics. Commercially available Nippon DLA and Green-cap supercapacitors were used to verify the Drude model by discharging them through a constant current source using a simple current mirror circuit. The parameters of both the fractional-order models and our suggested method were estimated using the leastsquares regression fitting approach. An intriguing finding from the Drude model is the currentdependent behavior of the leakage-parallel resistance in the constant current discharge process. Instead of using the traditional exponential rule, supercapacitors discharge according to a power law. This work reflects the strong symmetry of different aspects of designing a hybrid supercapacitor with high efficiency and reliability.
Research Interests:
Quantum-dot Cellular Automata (QCA) is an exciting new development in the field of nanoscale-based very large scale integration (VLSI) that has the potential to replace more conventional complementary metal oxide semiconductor (CMOS)... more
Quantum-dot Cellular Automata (QCA) is an exciting new development in the field of nanoscale-based very large scale integration (VLSI) that has the potential to replace more conventional complementary metal oxide semiconductor (CMOS) technology. In this article, a thorough and detailed description of the novel QCA based 5-input Majority gate is presented. In order to validate the accuracy of a 5-input majority gate, a comprehensive analysis has been carried out, taking into account the location of each and every QCA cell inside a structure. In this paper, a completely new 1-bit full-adder is constructed in order to assess the possible advantages offered by the recently developed 5-input majority gate. The comparative analysis with the reported designs in the literature revealed that the proposed full adder is superior in terms of cell count with a reduction of more than 54.79 %, as well as a decrease in area of more than 25 %, and a reduction in latency of 83.33 %. These findings were derived from the observation that the proposed full adder is better. For the purpose of demonstrating the usefulness and dependability of the strategy, power analysis have been carried out on the proposed full adder design using the QCAPro and QCADesigner 2.0.3 tools, respectively. The new majority gate technique is based on a variety of designs that enjoy the parameters of less area, durable circuit architecture, and optimal clock cycles, as well as the higher performance aspects associated with high-speed computation.
Research Interests:
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so on. Its primary... more
The Energy Storage System (ESS) is geared toward sophisticated systems with increased operating time for a variety of real-time applications such as an electric vehicle, a WSN (Wireless Sensor Network), a Capa bus, and so on. Its primary focus is on supplying these kinds of systems with additional capacity in recent development, and this will continue to be its primary focus. Because of their exceptionally high specific power, rapid charging, and low ESR (Effective Series Resistance), electric double-layer (EDLC) capacitors or supercapacitors are encouraged for use because they can be integrated more easily with battery technology that can be used in electric vehicles and other electronic devices. The supercapacitor calls for a precise and accurate characterization in order to facilitate the development of improved applications and more effective energy storage devices and technologies. In this article, we studied various supercapacitor electrode components, electrolytic solutions, analogous circuit models, electrical energy storage properties, and some real-time supercapacitor applications in the automotive, manufacturing, construction, and consumer electronics industries. In addition, we have discussed on hybrid material that was just recently developed with the goal of enhancing the conductivity and effectiveness of supercapacitors. Aside from this, we have discussed about the behaviour of supercapacitors in terms of how their behaviour is dependent on current and voltage with detailed analysis.
Research Interests:
Compared to metal-oxide-semiconductor field-effect transistors (MOS), the quantum-dot cellular automata (QCA) offer great advantages. This paper deals with the QCA implementation of digital circuits such as full adder, multiplexer,... more
Compared to metal-oxide-semiconductor field-effect transistors (MOS), the quantum-dot cellular automata (QCA) offer great advantages. This paper deals with the QCA implementation of digital circuits such as full adder, multiplexer, carry-save adder, carry-select adder, carry-skip adder, and barrel shifter for robust architecture in the nanoelectronics domain. The goal is to provide a framework for optimizing QCA designs utilizing coplanar cells that is also flexible enough to be used in complicated system design. As a result of this synthesis, the new design is appropriate for the creation of nanoelectronic circuits. The QCADesigner tool was used to verify the digital circuits in the synthesized designs presented in this article. The QCA simulation environment is used to verify designs, extract parameters, and perform digital computing. The primary goal of this study is to develop a robust adder design in terms of bounded box area and other cost primitives. The coplanar method is used to construct the QCA layouts of various adders, which is more efficient and compact. The comparison results have shown that the adoption of novel digital designs offers better results and provides a more robust architecture as compared to the literature works.
Research Interests:
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN... more
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Research Interests:
In continuous upgrading world, humans believe in their self-worth. They have participation in every sector of life, but lives have become so vulnerable these days that the safety and security of their lives are one of the burning... more
In continuous upgrading world, humans believe in their self-worth. They have participation in every sector of life, but lives have become so vulnerable these days that the safety and security of their lives are one of the burning questions about this pandemic corona virus disease. Considering all incidents and violation of rules do not spread against humanity this idea of a smart wristband safety device aligned with GPS and GSM modules, with temperature and pulse sensors came into consideration. During dangerous situations user just needs to press the
SOS button fitted on the wristband, or the sensors will sense an increase in temperature or pulse rate and then automatically the message of user location tracking via GPS will be sent to the registered numbers through GSM. The main objective is for the device to be light weight and
place the SOS switch in an easy accessible region, with additional sensors leaving no worse case possible.
SOS button fitted on the wristband, or the sensors will sense an increase in temperature or pulse rate and then automatically the message of user location tracking via GPS will be sent to the registered numbers through GSM. The main objective is for the device to be light weight and
place the SOS switch in an easy accessible region, with additional sensors leaving no worse case possible.
Research Interests:
MOS based circuits and computing devices are facing challenge related to energy dissipation, short channel effect and device density. The state of the art technology is driven towards Quantum cellular automata (QCA) computing with an... more
MOS based circuits and computing devices are facing challenge related to energy dissipation, short channel effect and device density. The state of the art technology is driven towards Quantum cellular automata (QCA) computing with an emphasis on a high-speed and smaller area. QCA is a new computing technology that is made of quantum cell restraining two electrons and two dots. In this paper, a novel design of Fredkin, Toffoli, and Feynman gate layout is designed using the molecular QCA concept. Presented cell layout of newly circuit
validity is verified by QCADesigner software. Further, a large number of articles are reviewed and comparison results are presented to show the optimal results such as cell count, majority gate count, bounded box area, and clock utilize. In this work, QCA and reversible logic combined together and the proposed designs have less bounded box area and delay, which is an essential part of the next-generation computing.
validity is verified by QCADesigner software. Further, a large number of articles are reviewed and comparison results are presented to show the optimal results such as cell count, majority gate count, bounded box area, and clock utilize. In this work, QCA and reversible logic combined together and the proposed designs have less bounded box area and delay, which is an essential part of the next-generation computing.
Research Interests:
The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison... more
The approach to designing digital circuits using three-dimensional (3D) perpendicular nanomagnetic logic (pNML) is thoroughly investigated. Nanomagnetic logic (NML) technology eventually optimizes the circuit performance in comparison with conventional metal–oxide–semiconductor (MOS) technology, which suffers from the hot carrier, velocity saturation, and short-channel effects, which may considerably degrade device performance. In contrast, nanomagnetic logic is immune to radiation; it behaves as nonvolatile memory and shows zero leakage current, as required for use in high-speed and low-cost nanoelectronics applications. In this paper, novel and organized designs, e.g., for 3D Ex-OR, parity generator, parity checker, multiplexer, and arithmetic logic unit (ALU) functionality, are synthesized using pNML technology. Previous designs are not compact in terms of delay, layer count, or bounded area. To overcome this, new designs for the mentioned functionalities are proposed based on pNML with smaller area and lower latency compared with previous circuits.
Research Interests:
In this paper, a new layout of the median filter by using Quantum-dot cellular automata (QCA) is designed. This filter is designed using one hot encoding technique. A new algorithm for designing median filter is proposed using majority... more
In this paper, a new layout of the median filter by using Quantum-dot cellular automata (QCA) is designed. This filter is designed using one hot encoding technique. A new algorithm for designing median filter is proposed using majority logic. The 1-bit median finding architecture occupies area of 0.05 µm 2 , with a delay of 0.5 clk. The proposed median finding architecture is also extended to higher bit sizes with optimized performance. The uniqueness of our n-bit median finding architecture is that for any bit size the delay for finding the median value is same which is 0.5 clk because every majority gates are working independently. Therefore for faster operation, this majority logic-based technology is highly congruous. All the QCA circuits are implemented in QCA Designer software.
Research Interests:
Nano-magnetic logic is one of the most competitive technologies of conventional metal oxide semiconductor-based designs. There is no current flow, and information is transferred via the magnetic force between the magnets. Because of this... more
Nano-magnetic logic is one of the most competitive technologies of conventional metal oxide semiconductor-based designs. There is no current flow, and information is transferred via the magnetic force between the magnets. Because of this phenomenon, it has low power dissipation and operating in the megahertz frequency range. In this paper, perpendicular nano-magnetic logic (pNML) technology is used for designing a non-restoring divider circuit. First, a new three-dimensional layout of the Exclusive-OR (XOR) gate is proposed. This layout is extended to a new 1-bit full adder circuit, 1-bit non-restoring cell and a 4-bit non-restoring divider. According to our insight, the proposed non-restoring divider circuit in the pNML layout and use of the multilayer is the first time in the literature. The areas of the proposed layouts are 9.72 µm2, 45.9 µm2, 61.2 µm2 and 3955.95 µm2 for the XOR gate, full adder, non-restoring cell and non-restoring divider designs, respectively. The proposed FA consumes 44.25% less latency and 60% fewer layers than the existing state-of-the-art work. All the proposed layouts are implemented using the MagCAD tool.
Research Interests:
Quantum cell automata (QCA) are the best possible alternative to the conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring.... more
Quantum cell automata (QCA) are the best possible alternative to the
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and 4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in the square than in other competitive square circuits such as Wallace, Dadda, serial parallel, and Baugh-Wooley.
conventional CMOS technology due to its low power consumption, less area and high-speed operation. This paper describes synthesizable QCA implementation of squaring. Vedic sutras used for squaring are defined over algorithm construction. Based on the concept of the Vedic sutra, this paper has carried out 2-bit square and 4-bit square, projective to affine logic gates construction. Importantly for miniaturization
of devices, the QCA based square is the operation on which the area of
circuits relies on. This means that significantly lower QCA parameters can be used in the square than in other competitive square circuits such as Wallace, Dadda, serial parallel, and Baugh-Wooley.
Research Interests:
The CMOS-based integrated circuit may scale down to nanometer range. The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way,... more
The CMOS-based integrated circuit may scale down to nanometer range.
The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way, the state-of-the-art technology such as QCA was forced toward high-speed computing with negligible energy dissipation in the physical foreground. This work targets the design of non-restoring reversible divider circuit and its implementation
in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block
construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates and QCA implementation. This divider circuit inherits many benefits such as fewer garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider
also compares the reversible metrics results with some of other existing works.
The primary challenge is to further downscale the device and high-energy dissipation. Reversible logic does not dissipate energy and no information loss. In this way, the state-of-the-art technology such as QCA was forced toward high-speed computing with negligible energy dissipation in the physical foreground. This work targets the design of non-restoring reversible divider circuit and its implementation
in QCA. We have utilized few 2 × 2 FG and 4 × 4 HNG gates as the block
construction and also show the QCA implementation having cost-efficient approach. Further, the divider circuit has synthesized with FG and HNG gates and QCA implementation. This divider circuit inherits many benefits such as fewer garbage outputs, reduce quantum cost are achieved, and also reduced QCA primitives can be improved by using efficient QCA layout scheme. Simulation investigations have been verified by QCA Designer. The proposed non-restoring divider
also compares the reversible metrics results with some of other existing works.
Research Interests:
In this era of emerging technology, fault-tolerant logic is applied for circuit design. As the deep submicron and scaling, a number of pitfalls are the faces of the CMOS technology. So a lot of constraints related to CMOS have shorted... more
In this era of emerging technology, fault-tolerant logic is applied for
circuit design. As the deep submicron and scaling, a number of pitfalls are the faces of the CMOS technology. So a lot of constraints related to CMOS have shorted with the quantum-dot cellular automata (QCA) technology. In this work, a new parity conservative gate referred as parity-QCA (P-QCA) is proposed. The gate is simulated with QCADesigner and compared with existing parity preserving logic
gates. By the comparative outcomes, it is found that the proposed design achieved higher efficiency as compared to the counterparts. We achieved 100% stuck-at fault coverage.
circuit design. As the deep submicron and scaling, a number of pitfalls are the faces of the CMOS technology. So a lot of constraints related to CMOS have shorted with the quantum-dot cellular automata (QCA) technology. In this work, a new parity conservative gate referred as parity-QCA (P-QCA) is proposed. The gate is simulated with QCADesigner and compared with existing parity preserving logic
gates. By the comparative outcomes, it is found that the proposed design achieved higher efficiency as compared to the counterparts. We achieved 100% stuck-at fault coverage.
Research Interests:
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting success. The introduced architecture is robust where the explicit design of full adder... more
Moving towards micrometre scale to nanometre scale device shrinks down emerging nanometre technology such as quantum-dot cellular automata as a nesting success. The introduced architecture is robust where the explicit design of full adder and full subtraction uses forEx-ORdesign.Anewarchitecture ofEx-OR based on one majority gate is proposed, which its most optimized architecture and its placement
of cells from the novel design. The analysis based on simulation showed that the introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In proposed Ex-OR design, first output is received with no any latency which can be a suitable design for implementation of the high-speed full adder design. In addition, power estimation results are obtained after simulation of proposed designs inQCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
of cells from the novel design. The analysis based on simulation showed that the introduced Ex-OR and full adder makes only 11 and 46 cells count, respectively. In proposed Ex-OR design, first output is received with no any latency which can be a suitable design for implementation of the high-speed full adder design. In addition, power estimation results are obtained after simulation of proposed designs inQCAPro
tool. Therefore, the novel designs improve the energy dissipation parameters such as mean leakage energy dissipation, mean switching energy dissipation and total energy dissipation 75, 11.28 and 82.19% in comparison with the most robust design in existing.
Research Interests:
Reversible logic has gained importance in the present development of low-power and high-speed digital systems in nanotechnology. In this manuscript, we have introduced and optimized the reversible Binary to Gray and Gray to Binary code... more
Reversible logic has gained importance in the present development of
low-power and high-speed digital systems in nanotechnology. In this manuscript, we have introduced and optimized the reversible Binary to Gray and Gray to Binary code converters circuit using two new types of reversible gates. Two new types of 3 × 3 reversible gates, namely BG-1 gate (Binary to Gray) and GB-1 gate (Gray to Binary), have been proposed to design converter circuits without any garbage outputs. In addition, useful theorems have been developed, associated with the number of gates, garbage outputs, constant input and quantum cost of the reversible converters. The QCA Designer v2.0.3 tool is used for simulation to test the workability of reversible code converters. The simulation results show that the design works correctly and extracted parameters are better than the previously reported designs. Area and lower bound parameter analysis also show that the design is based on the optimized approach.
low-power and high-speed digital systems in nanotechnology. In this manuscript, we have introduced and optimized the reversible Binary to Gray and Gray to Binary code converters circuit using two new types of reversible gates. Two new types of 3 × 3 reversible gates, namely BG-1 gate (Binary to Gray) and GB-1 gate (Gray to Binary), have been proposed to design converter circuits without any garbage outputs. In addition, useful theorems have been developed, associated with the number of gates, garbage outputs, constant input and quantum cost of the reversible converters. The QCA Designer v2.0.3 tool is used for simulation to test the workability of reversible code converters. The simulation results show that the design works correctly and extracted parameters are better than the previously reported designs. Area and lower bound parameter analysis also show that the design is based on the optimized approach.
Research Interests:
The reversible logic circuit is popular due to its quantum gates involved where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is... more
The reversible logic circuit is popular due to its quantum gates involved
where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is designed, and effect of reversible metrics is analyzed such as gate count, ancilla input, garbage output, and quantum cost. This design can build blocks of basic existing parity preserving reversible gates. The building blocks of the code converter reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
where quantum gates are reversible and noted down feature of no information loss. In this paper, parity preserving reversible binary-to-BCD code converter is designed, and effect of reversible metrics is analyzed such as gate count, ancilla input, garbage output, and quantum cost. This design can build blocks of basic existing parity preserving reversible gates. The building blocks of the code converter reversible circuit constructed on Toffoli gate based as well as elemental gate
based such as CNOT, C-V, and C-V+ gates. In addition, qubit transition analysis of the quantum circuit in the regime of quantum computing has been presented. The heuristic approach has been developed in quantum circuit construction and the optimized quantum cost for the circuit of binary-to-BCD code converter. Logic functions validate the development of quantum circuit. Moving the testability aim are figured in the quantum logic circuit testing such as single missing gate and single missing control point fault.
Research Interests:
This work, we employ computing around quantum-dot automata to construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres gate,... more
This work, we employ computing around quantum-dot automata to
construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres gate, respectively. We have presented the robust design of Ex-OR in QCA, which is used for the construction of code converters and binary incrementer. The layouts of proposed circuits were made using the primary elements such as majority gate,
inverter, and binary wire. A novel binary-to-gray converter design offers 59% cell count reduction and 36% area reduction in primitives improvement from the benchmark designs. Being pipeline of PG gate to construct the 1-bit, 2-bit, and 3-bit binary incrementer, we can use this robust layout in the QCA implementation of binary incrementer. By the comparative result, it is visualized that the binary incrementer such as 1-bit, 2-bit, and 3-bit achieved 60.82, 60.72, and 64.79% improvement regarding cell count from the counterpart.
construct the architecture of the reversible code converters and binary incrementer. The code converter and binary incrementer are made up of Feynman gate and Peres gate, respectively. We have presented the robust design of Ex-OR in QCA, which is used for the construction of code converters and binary incrementer. The layouts of proposed circuits were made using the primary elements such as majority gate,
inverter, and binary wire. A novel binary-to-gray converter design offers 59% cell count reduction and 36% area reduction in primitives improvement from the benchmark designs. Being pipeline of PG gate to construct the 1-bit, 2-bit, and 3-bit binary incrementer, we can use this robust layout in the QCA implementation of binary incrementer. By the comparative result, it is visualized that the binary incrementer such as 1-bit, 2-bit, and 3-bit achieved 60.82, 60.72, and 64.79% improvement regarding cell count from the counterpart.
Research Interests:
As a semiconductor industry continues growing toward miniaturization and high speed, it is challenged by the rising uncertainties in the scaling for further devices shrink in the nanometer scale. Scaling leads to quantum effect at the... more
As a semiconductor industry continues growing toward miniaturization
and high speed, it is challenged by the rising uncertainties in the scaling for further devices shrink in the nanometer scale. Scaling leads to quantum effect at the nanoscale. Quantum dot cellular automata (QCA) is the alternative approach to synthesize the digital logic circuits with high density and high computation speed. In this paper, an accurate approach to synthesize and optimize the Baugh-Wooley multiplier and non-restoring divider in the presence of QCA technology has been
proposed. The proposed designs are robust and utilize a wire-crossing type of single layer, with minimal clock phasing. The synthesis approach and optimization are perfectly scalable across layout construction of designs and can find better primitive’s results of QCA circuit performance.
and high speed, it is challenged by the rising uncertainties in the scaling for further devices shrink in the nanometer scale. Scaling leads to quantum effect at the nanoscale. Quantum dot cellular automata (QCA) is the alternative approach to synthesize the digital logic circuits with high density and high computation speed. In this paper, an accurate approach to synthesize and optimize the Baugh-Wooley multiplier and non-restoring divider in the presence of QCA technology has been
proposed. The proposed designs are robust and utilize a wire-crossing type of single layer, with minimal clock phasing. The synthesis approach and optimization are perfectly scalable across layout construction of designs and can find better primitive’s results of QCA circuit performance.
Research Interests:
Recently, Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention... more
Recently, Quantum-dot Cellular Automata (QCA) based reversible logic circuit has an enormous benefit over CMOS based logic circuit. As a promising technology for Nanoelectronics computing, reversible-QCA has gained more and more attention from researchers around the world. In this paper, a reversible authenticator circuit based on QCA was implemented. This article presents a Nano-authenticator circuit to verify the authenticated and unauthenticated inputs. The proposed QCA designs have been implemented in a different manner from existing designs, which are primarily based on a coplanar design approach. The efficiency of QCA design has been investigated based on parameters such as cell count, area, and latency. Furthermore, missing an additional cell defect of the reversible authenticator has been analyzed, and covers the fault tolerance of 60.41% and 75%, respectively. In addition, the proposed Feynman gate in QCA environment achieves 76.35% area, 12.5% cell count and 95.55% average energy dissipation improvement as compared to the existing layout. Moreover, the new reversible authentication circuit achieves 87.75% cost and 43.54% area improvement in comparison with the previous state-of-art design.
Research Interests:
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the... more
Restoring and non-restoring divider has become widely applicability in the era of digital computing application due to its computation speed. In this paper, we have proposed the design of divider of different architecture for the computation of Vedic sutra based. The design of divider in the Vedic mode results in high computation throughput due to its replica architecture, where latency is minimized in each of the
replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the architecture of cell by using the robust design computing architecture. For the extended perspective of lower divider to higher divider and to synthesize, target outcomes by using efficient architecture.
replica stages. The proposed novel divider based symmetric key crypto-hardware architecture for lightweight embedded devices and the results obtained for this architecture by the analysis using the QCADesigner tool. For the physical environment in QCA computing paradigm are achieved through optimization the architecture of cell by using the robust design computing architecture. For the extended perspective of lower divider to higher divider and to synthesize, target outcomes by using efficient architecture.
Research Interests:
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on... more
Nano Magnetic Logic (NML) has been attracting application in optical computing, nanodevice formation, and low power. In this paper nanoscale architecture such as the decoder, multiplexer, and comparator are implemented on perpendicular-nano magnetic logic (pNML) technology. All these architectures with the superiority of minimum complexity and minimum delay are pointed. The proposed architectures have been designed using pNML in MagCAD tool, simulated with modelsim platform and correctness shown by simulation waveform. The correctness of these designs can be verified easily when Verilog code is generated from MagCAD tool. The performance of the proposed comparator towards default parameters shows the area of 2.4336 μm2 and critical path of 1.5E-7 sec. As a higher order, the realization of a 4-to-1 multiplexer in NML has also been included in this work.
Research Interests:
Day to day VLSI circuit is becoming more complex in regard of architecture and analysis point of view. A high computation design with less power consumption and miniaturization in the area is implicit to the current semiconductor... more
Day to day VLSI circuit is becoming more complex in regard of architecture and analysis point of view. A high computation design with less power consumption and miniaturization in the area is implicit to the current semiconductor industry. In these, a methodology for error-control parity generator and checker is fundamental of data communication and widely used in error control application. In this paper is the synthesis of the parity generator and checker, which has the unique architecture in terms of architecture complexity. Efficiency in terms of the VLSI performance attributes such as delay, power, and area. Then with the use of GDI technique a new architecture of parity generator and checker is introduced, we achieved a design with low supply voltage operation. The 3-bit parity generator and checker based on GDI technique is successful, simulated and tested at 0.5V, 1V, 1.5V, 2V supply voltage and consumed power at these voltages are 5µw, 2.5µw, 3.3µw and 0.2ns, 0.3ns, and 0.8ns worst condition of delay respectively.
Research Interests:
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal (BCD) adder is proposed for the quantum... more
Reversible logic has been recognized as one of the most promising technique for the realization of the quantum circuit. In this paper, a cost effective conservative, reversible binary coded decimal (BCD) adder is proposed for the quantum logic circuit. Towards the realization of BCD adder, few novel gates, such as Half-Adder/Subtraction (HAS-PP), Full-Adder/Subtraction (FAS-PP) and Overflow-detection (OD-PP) based on parity preserving logic are synthesized which incurs 7, 10 and 13 quantum cost respectively. Coupling these gates a novel tree-based methodology is proposed to implement the required BCD Adder. Also, the BCD adder design has been optimized to achieve the optimum value of quantum cost. In addition, the proposed BCD circuit is extended to n-bit adder using replica based techniques. Experimental result establishes the novelty of the proposed logic, which outperforms the conventional circuits in terms of logic synthesis and testability. The limitation of detecting the missing gate and missing control point of the quantum circuit of overflow detection is finally tackled this work by the proposed OD-PP with the application of the minimum test vector. In addition, reversible circuits of control inputs based testable master-slave D-FF is intended. The noted work on the testable sequential circuit presented here is to develop circuit using minimum test vectors and can find diverse application in the testing paradigm.
Research Interests:
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a conservative reversible... more
The quantum-dot cellular automata (QCA) has more advantages than CMOS regarding area and power. This work targets a conservative reversible comparator and its realization in QCA. In this work, we construct a conservative reversible comparator with an optimal value of reversible metrics. In state to design, three conservative reversible gates, namely PPC, PPNG-1 and PPNG-2 (PP = parity-preserving, C = comparator, N = new, G = gate), are proposed. Furthermore, the quantum equivalent of 1-bit and 2-bit comparator is presented. The proposed concept has been implemented through an algorithm for the n-bit comparator. Also, PPC workability is tested in QCA. The PPC has been performing 1-bit comparator result with minimum area, cell complexity, and latency, which is found to be 0.52 μm2, 387 and 1 respectively. In addition, the complete energy dissipation analysis to explore such as a thermal layout map of PPC is also presented in this paper. Further, average energy dissipation v's kink energy, maximum energy dissipation v's kink energy, minimum energy dissipation v's kink energy and average output node polarization v's temperature are provided in this paper. The proposed comparator forwards an improved ratio of 33.33% in gate count and ranging from 27.27% to 29.35% in garbage outputs than its counterparts circuits, which ensure more scalable.
Research Interests:
Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum... more
Reversible logic has attracted interest from many researchers in the area of quantum information science. Since there is no information loss in reversible logic, energy consumption is greatly reduced. However, realization of quantum equivalent circuits using cascading reversible gates is complex. Predominantly, this work targets implementation of quantum equivalent circuits using cascading reversible gates. In this work, novel code converters and a dual-rail checker with lower cost metrics such as gate count, garbage output, ancilla input, unit delay, logical calculation, and quantum cost are constructed. Several new reversible gates, namely BE (binary excess), BG-2 (binary Gray), GB-2 (Gray binary), and NG-R1 and NG-R2 (N == new, R == reversible), are designed and used to construct efficient code converter and dual-rail checker circuits. The main contribution of these novel circuits is the consideration of the gate-level schematics in the respective quantum equivalent circuit using our proposed algorithm. The performance results establish that the novel binary-coded decimal (BCD)-to-excess-3, binary-to-Gray, and dual-rail checker achieve improvement of 25 and 66.6 % in gate count and 44.4 % in quantum cost, respectively, compared with counterpart designs.
Research Interests:
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in... more
The CMOS faces challenges related to the increment in leakage-current to power-consumption. QCA is a promising alternative to overcome these challenges successfully. On the other hand, reversible logic plays a significant role in quantum-computing. Keeping this technique in mind, a conservative-reversible flip-flops and counter are explored here which will bring QCA and reversible computing together in a single-platform. In synthesizing, a reversible-conservative-quantum-cellular-automata (R-CQCA) is proposed. The proposed D, T, JK and dual-edge master-slave flip-flops advocate an improvement of 20%, 46.6%, 50%, and 36.66% respectively than its counterpart in quantum-cost. Further, the 100% fault-coverage by stuck-fault is framed in R-CQCA, which can be useful for a tester to maintain data-integrity. Also, the R-CQCA layout is implemented in QCA, which achieve some parameters such as cell-complexity of 177, leakage-energy-dissipation of 0.1055 eV, and size of 0.24 mm 2. Moreover, R-CQCA is better than FRG, RM, PPRG and MX-cqca regarding QCA-primitives are reported here. One of the major limitations of CMOS technology is its high power consumption. This problem cannot be completely solved even by further scaling the size of the transistor. A possible solution is to develop new computational paradigms based on quantum technologies. In this way, the reversible logic technique is a primary part of quantum technology because of the unitary property of quantum computations [1]. They enormously deal with low energy dissipation. Landauer [1] pointed that logic computation that is non-reversible essentially dissipates heat energy. Bennett [2] pointed that no energy dissipation is possible only if a design includes reversible gates. The feature of reversible gates bijections property from the input states to the output states, and have consequently recovered outputs from inputs. The primary abstract behind the conservative logic of the observable operations for the manipulation of Ex-OR of the inputs and outputs. In fact, conservative reversible logic is an equal hamming weight used in inputs and outputs to ensure the observance of testability [3]. The novelty of the proposed designs around quantum computing paradigm is the realization of a quantum equivalent of a sequential circuit with low quantum cost. Sequential circuits are the fundamental parts in various digital VLSI circuits such as memory, general purpose register and accumulation for the processor. In this paper, we target on synthesizing conservative reversible (CR) flip-flops and Binary-coded decimal (BCD) ripple counter with low quantum cost (QC) using R-CQCA, which will be illustrated in Sec. 4. The proposed circuits focus on the quantum equivalent realization (QER) through some additional coding in RCviewer+ tool. The exact QC are obtained after QER of the circuit. The construction of QER from the elementary gates such as CNOT, NOT, C-V, and C-V +. A new R-CQCA gate strongly alters the circuit cost of reversible sequential circuits. The proposed circuits more competent and best suitable for such as general purpose register and the memory element. The proposed gate R-CQCA has a wide utility such as universal gates (NAND, NOR), multiplexer (mux), flip-flops (FFs), and counter. The proposed R-CQCA contains only 6 quantum cost (QC), very few conservative reversible gates (CRGs) that have such value of the QC. This work includes the following contributions: We designed a low QC, R-CQCA for NANO-Electronics application. We present the QCA robust structure of R-CQCA, and the simulation outcomes specify the correct functionality and also the low worst case latency of 2.5 is reported here.
Research Interests:
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power... more
In the digital circuit design, the primary factors are low power and a high packing density. The reversible logic circuit in quantum-dot cellular automata (QCA) framework is hoped to be effective in addressing the factor of power consumption at nanoscale regime. Fault tolerant circuits are suited of
interruption of errors at the outputs. This manuscript focuses the design of ALU
in QCA-based and propose new parity preserving gate. It has been introduced
that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
interruption of errors at the outputs. This manuscript focuses the design of ALU
in QCA-based and propose new parity preserving gate. It has been introduced
that new reversible gate, namely, universal parity preserving gate (UPPG), to optimise the ALU circuits. An algorithm and lemmas are shown in designing ALU. The ALU generates a number of arithmetic and logical function with using only less architectural complexity. Most importantly circuit design
focuses on optimising the gate count and quantum cost. In addition to optimisation, the workability of UPPG gate is tested by QCA and the simulation result obtained ensures the correctness of the design.
Research Interests:
Now a day's reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic... more
Now a day's reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic from an output logic because of bijective mapping between input and output. In this manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative study shows that the proposed compressor structure outperforms the existing ones in terms of garbage outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS transistor with less number of MOS transistor count.
Research Interests:
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic... more
Now a day’s reversible logic is an attractive research area due to its low power consumption in the area of VLSI circuit design. The reversible logic gate is utilized to optimize power consumption by a feature of retrieving input logic from an output logic because of bijective mapping between input and output. In this manuscript, we design 4:2 and 5:2 reversible compressor circuits using a new type of reversible gate. In
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS transistor with less number of MOS transistor count.
addition, we propose new gate, named as inventive0 gate for optimizing a compressor circuit. The utility of the inventive0 gate is that it can be used as full adder and full subtraction with low value of garbage outputs and quantum cost. An algorithm is shown for designing a compressor structure. The comparative study shows that the proposed compressor structure outperforms the existing ones in terms of garbage
outputs, number of gates and quantum cost. The compressor can reduce the effect of carry (Produce from full adder) of the arithmetic frame design. In addition, we implement a basic reversible gate of MOS transistor with less number of MOS transistor count.
Research Interests:
As per the circuit complexity is increased there is a need of advancement of technology by using reversible logic. The circuit complexity comprises number of gate, size, power, delay and other parameters. Furthermore, error control... more
As per the circuit complexity is increased there is a need of advancement of technology by using reversible logic. The circuit complexity comprises number of gate, size, power, delay and other parameters. Furthermore, error control methodology is required in reversible area which processes input, maintains data integrity, testing, error detection and checking the required output. The various approaches are categorized for error control which are significantly different and provides optimized solutions. In this paper, we design a various compact circuits related to error control schemes. Two 4x4 reversible series gates, namely inventive gate and inventive Parity preserving gate are introduced, to optimize the various error control circuits. We also introduced feasible methodology of concurrent error detection (CED), hamming single bit error correction (SBEC) and double bit error detection (DBED), 23×3 priority encoder circuit and dual rail checker circuit with parity- preserving behavior all with its detailed algorithm.
Research Interests:
A large amount of research is currently going on in the field of reversible logic, which have low heat dissipation, low power consumption, which is the main factor to apply reversible in digital VLSI circuit design.This paper introduces... more
A large amount of research is currently going on in the field
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
of reversible logic, which have low heat dissipation, low
power consumption, which is the main factor to apply
reversible in digital VLSI circuit design.This paper introduces
reversible gate named as ‘Inventive0 gate’. The novel gate is
synthesis the efficient adder modules with minimum garbage
output and gate count. The Inventive0 gate capable of
implementing a 4-bit ripple carry adder and carry skip adders.
It is presented that Inventive0 gate is much more efficient and
optimized approach as compared to their existing design, in
terms of gate count, garbage outputs and constant inputs. In
addition, some popular available reversible gates are
implemented in the MOS transistor design the implementation
kept in mind for minimum MOS transistor count and are
completely reversible in behaviour more precise forward and
backward computation. Lesser architectural complexity show
that the novel designs are compact, fast as well as low power.
Research Interests:
Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using... more
Reversible logic has attracted substantial interest due to its low power consumption which is the main
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
concern of low power VLSI systems. In this paper, a novel 4x4 reversible gate called inventive gate has
been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator
have been constructed with low value of reversible parameters. The MOS transistor realizations of 1-bit, 2-
bit, and 8-bit of reversible comparator are also presented and finding power, delay and power delay
product (PDP) with appropriate aspect ratio W/L. Novel inventive gate has the ability to use as an n-to-2n
decoder. Different novel reversible circuit design style is compared with the existing ones. The relative
results shows that the novel reversible gate wide utility, group-based reversible comparator outperforms
the present style in terms of number of gates, garbage outputs and constant input.
Research Interests:
The model of computing in which the computational progression is reversible or to some extent time inverting is entitled reversible computing. In the modern epoch reversible logic has materialized as a promising, competent technology... more
The model of computing in which the computational progression is reversible or to some extent time inverting is entitled reversible computing. In the modern epoch reversible logic has materialized as a promising, competent technology comprising its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The conventional gates such as AND, OR, and EXOR are not reversible. Here in this manuscript we put forward a 4*4 reversible gate design called “NSG”. The most noteworthy, considerable attribute of the proposed gate is that it can work individually as a reversible full adder, reversible full subtractor, reversible half adder, and reversible half subtractor. That is now we are capable of implementing reversible full adder, subtractor and reversible half adder, subtractor with a single gate only. The proposition of this meticulous manuscript is a design a parity preservation property using NS Gate.
Research Interests:
Research Interests:
Research Interests:
Research Interests:
The objective of this work is “DESIGN AND DEVELOPMENT OF EFFICIENT SRAM CELL BASED ON FINFET FOR LOW POWER MEMORY APPLICATIONS” The need for battery driven equipment is increasing each day like in sensors, wireless gadgets, cell phones... more
The objective of this work is “DESIGN AND DEVELOPMENT OF EFFICIENT SRAM CELL BASED ON FINFET FOR LOW POWER MEMORY APPLICATIONS” The need for battery driven equipment is increasing each day like in sensors, wireless gadgets, cell phones and medical implants. It is required that these equipment consume less power during their operation to enhance the battery life. Hence to address this problem, there is a requirement for such a device that can handle the co-existence of low voltage and low power handling capacity. The work in this book has been carried out to suggest solutions to these challenges by proposing and implementing a novel device for both analog and digital applications .In this book, a low power and high performance 3D Quad Gate Stacked Nano-sheets FinFET (QG-SNS) device has been designed by adding an additional fourth gate to a tri-gate device and it has been modified to make fins as vertically stacked Nano-sheets. The prerequisite is that the physical parameters must have been calibrated. The designed device has been calibrated and optimized at 30 nm technology node on COGENDA Visual TCAD tool and Visual Fab tool. Simulations have been performed for VGS varying from 0 Volt to 1 Volt. The voltage at drain terminal is kept at 0.05 Volt and 1 Volt for linear and saturation modes respectively.
Research Interests:
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet... more
The impact of quantum computing has been widely recognised in the engineering domain. The age of quantum computing has arrived, and with it comes the ability to easily solve exponential problems. This book is written by me to meet current academic demands. The book is designed to address the most important aspects of the subject of Quantum Computing. The publication of the book "Quantum Computing" is the culmination of numerous years of research and teaching in academia. It is given in a way that is straightforward to comprehend. The undergraduates, and graduate students may all benefit from reading this book. We have given our very best effort to bring you accurate book material.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
The book explains the fundamentals of this topic in simple, straightforward language. The most efficient approach to go through this book is to grasp the underlying fundamental as well as mathematical concepts. The chapters are meant to stand on their own. This book is not intended to be theoretical; rather, it will serve to familiarise you with the fundamental of quantum computing, like applications, multiple-qubit systems, quantum state transformations, quantum gates and quantum circuits, tools for quantum computing, bell states, quantum Parallelism, quantum Algorithms: Shor’s Algorithm, Grover’s Algorithm, Quantum Hardware and software, Quantum Cryptography and Security, Quantum Error Rates and Quantum Noise, Quantum Fourier Transform, Quantum Machine Learning and so on.
The model questions and multiple-choice questions that are provided at the end of the book have been chosen to improve readers' understanding, as well as their performance in exams and key employment.
We warmly welcome and would be very appreciative of any comments or recommendations, that will help us enhance the overall quality of the book.
Research Interests:
The aim of this novel work is to fill a gap that has appeared in the reversible computing, emerging domain of Futuristic Quantum Information Science. Themes in Quantum Information Science have been an emerging domain. This work targets... more
The aim of this novel work is to fill a gap that has appeared in the reversible computing, emerging domain of Futuristic Quantum Information Science. Themes in Quantum Information Science have been an emerging domain. This work targets the basic level void by terminology coverage of quantum circuit synthesis. Chapters introduce the synthesis approach of reversible adders, comparator, code converters, and median filter. This book then covers decomposition, mapping and optimization tools in quantum logic circuits. The flow of the work is organized to understand the synthesis of a quantum circuit that begins using quantum gates and then move into physical implementation on nano-computing technology.
The authors of this work realized a need for a conservative reversible nanocircuit which can involve quantum computing to researchers and other having a requirement for a cognizance of the emerging field, and the work attempts to meet... more
The authors of this work realized a need for a conservative reversible nanocircuit which can involve quantum computing to researchers and other having a requirement for a cognizance of the emerging field, and the work attempts to meet that need. The book beginnings with a basic to the topic of quantum computing. Followed by one supporting chapters on quantum computing and testing. Nanocircuit design for the low-cost nano-communication framework is addressed in two chapters; one on error control, decoder and the other on testing reversible logic circuit. This leads to another contribution of this work in that synthesis, optimization, testing of reversible circuits, quantum circuit, and logic around quantum-dot cellular automata build through the chapters. A Verilog code describes the algorithm of the HDLQ model components including all elements for the reversible gate is available for the readers. We hope that researchers and instructors find this book useful in their basic learning resource.
Research Interests:
In the present work of xilinx HDLC controller.HDLC operates at the data link layter of the OSI model main focus of the is to understand to the layer above it i.e is the network layer and layer below it ie physical layer.The function of... more
In the present work of xilinx HDLC controller.HDLC operates at the data link layter of the OSI model main focus of the is to understand to the layer above it i.e is the network layer and layer below it ie physical layer.The function of this protocol controller is to perform a number of separate activities like physical addressing to check the erors, flow control design of HDLC controler and simulation design and implement a high performance.This will be coded in a hardware description language VHDL
Research Interests:
This study applies the Taguchi orthogonal array (OA) to improve and optimize the performance of ZnO thin-film transistors (TFT). Radiofrequency (RF) sputtering method was used to deposit the active layer of TFTs. The annealing... more
This study applies the Taguchi orthogonal array (OA) to improve and optimize the performance of ZnO thin-film transistors (TFT). Radiofrequency (RF) sputtering method was used to deposit the active layer of TFTs. The annealing temperature, environmental conditions, sputter rate, and thin-film thickness were the parameters whose impact on output parameters like mobility was analyzed in the process optimization using design of experiment (DOE). The ZnO TFTs show state-of-the-art performance features, including high saturation mobility (0.83c), high Ion/Ioff ratio (104). The optimal configuration was found to be high annealing temperature 450 °C under N2 atmosphere, low sputter rate. This paper presents a method that can empower the fast optimization of metal oxide TFTs for future developments in the manufacturing process. If a full factorial design had been implemented, 64 tests would have been necessary, however in this work, we have reduced the number of tests to 9 only using Taguchi method.
Day by day, the energy storage system (ESS) has become critical due to its massive applications in real time, like a hybrid car, WSN (Wireless Sensor Network), a Capa bus, etc. The supercapacitor is gaining popularity in this relation... more
Day by day, the energy storage system (ESS) has become critical due to its massive applications in real time, like a hybrid car, WSN (Wireless Sensor Network), a Capa bus, etc. The supercapacitor is gaining popularity in this relation because of high power density, low ESR (Effective Series Resistance) and rapid charging with a longlife cycle, which makes supercapacitor a hot subject for research. This paper aggregates different researchers' works on the basis of fractographic study of electrode material of supercapacitor, and also discusses characterisation of the electrical and mechanical properties of aerographite/epoxy composites under tensile load. The combined analysis of all these fractographic studies, electrical and mechanical properties help to understand the behaviour of the supercapacitor, which also throws light to enhance the capability and applicability of the supercapacitor in the real-life system.
Research Interests:
CMOS technology is experiencing power dissipation, short channel effects and quantum effects problems with its relation to chip size, which makes it too hard for integrating more transistors, reaching its scaling limits. Quantum Dot... more
CMOS technology is experiencing power dissipation, short channel effects and quantum effects problems with its relation to chip size, which makes it too hard for integrating more transistors, reaching its scaling limits. Quantum Dot Cellular Automata (QCA) is one of emerging nanotechnologies in recent times to overcome this flaw. The QCA technology is used for designing and implementation of digital circuits efficiently due to its features like smaller feature size, high speed, low power dissipation and high switching frequency. These characteristics prompt memory cell architecture and implementation in QCA as an appealing choice for manufacturing storage devices. This paper discusses architectures of several line and loop based memory cells to compare in terms of density, low power, complexity and switching frequency and to deduce an architecture method which is significant for designing memory cells
Research Interests:
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of... more
Quantum-dot Cellular Automata is an alternative to CMOS technology for the future digital designs. When compared to its CMOS counterpart, it has extremely low power consumption, as there is no current flow in cell. The methodology of parity generator and checker is based on the parity generation and matched it at the receiver end. By using the parity match bits, the error in circuit can be sensed. In this paper, novel parity generator and detector circuit are introduced. The circuit is designed in single layer, minimum clock and minimum latency, which is achieved in QCA framework. The proposed circuits are better than the existing in terms of clock cycle delay, cell complexity and clock cycle utilize. The simulation of presented cell structures have been verified using QCA designer tool. In addition, QCA Probabilistic (QCAPro) tool is used to calculate the minimum, maximum and average energy dissipation aspect in proposed QCA circuit. Appropriate comparison table and power analysis is shown to prove that our proposed circuit is cost effective.
Research Interests:
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot Cellular Automata (QCA) which is widely utilized in nanocomputing era. QCA has Landauer clocked based synthesis approach and it has clocked based information... more
One of the critical issues in VLSI circuit is High Power dissipation. Quantumdot
Cellular Automata (QCA) which is widely utilized in nanocomputing era.
QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital
circuits in an emerging QCA framework. The design is evaluated and
formulated in terms of area, latency and power dissipation. QCA Designer
tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis
that the QCA based combination circuits will make a contribution to high
computing speed and low power paradigm.
Cellular Automata (QCA) which is widely utilized in nanocomputing era.
QCA has Landauer clocked based synthesis approach and it has clocked based
information flow. This manuscript analysis and design a combinational digital
circuits in an emerging QCA framework. The design is evaluated and
formulated in terms of area, latency and power dissipation. QCA Designer
tool has been taken for the design of quantum cell-based combinational circuits
and simulation purpose. Moreover, it is believed based on experimental analysis
that the QCA based combination circuits will make a contribution to high
computing speed and low power paradigm.
Research Interests:
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high density... more
Quantum-dot cellular automata is a nanoscale computation circuit design approach which computes bits via charges among quantum-dot in the quantum cell of QCA. This technology has promises the feature of energy efficient and high density in the era of high-speed nanotechnology. This article contributes a new nanoscale design of binary comparator with less latency, area, and clock utilized. The proposed comparator architecture is robust and enjoys wire crossing without any crossover, which needs only normal and rotated cells. All the simulation results and calculated parameters
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has been achieved and good contribution in this area.
are based on the QCADesigner tool. QCAPro tool based approach has been used to perform the energy dissipation estimation of the new comparator architecture. A better primitives results as compared to state-of-art technology has been achieved and good contribution in this area.
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error... more
Quantum-dot cellular automata are a prominent part of the nanoscale regime. They use a quantum cellular based architecture which enables rapid information process with high device density. This paper targets the two kinds of novel error control circuits such as Hamming code, parity generator and checker. To design the HG-PP HG = Hamming gate, PP = parity preserving, NG-PP NG = new gate are proposed for optimising the circuits. Based on the proposed gates and a few existing gates, the Hamming code and parity generator and checker circuits are constructed. The proposed gates have been framed and verified in QCA. The simulation outcomes signify that their framed circuits are faultless. In addition to verification, physical reversible is done. The reversible major metrics such as gate count, quantum cost, unit delay, and garbage outputs, uses best optimisation results compared to counterparts. They can be utilised as a low power error control circuit applied in future communication systems.
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Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer scale with high integration density, and significant low power. For the QCA technology, making these high-density design means an increase in... more
Quantum-dot cellular automata is a modern computing paradigm, conceived in feature of nanometer scale with high integration density, and significant low power. For the QCA technology, making these high-density design means an increase in the complexity which in turn leads to growth in the number of faults. The defect model presented in this paper categorized into two types, which include single missing and additional cell considering for QCA fault. Proposed gates have been designed in the QCA and verified. The proposed Fredkin gate design has been compared with an existing design, and 43% and 70% improvement in cell count and area respectively are revealed. Also, the Toffoli design in QCA which achieve some parameters such as cell complexity of 39, and the average fault tolerance of 53.5%. The polarization value for both single cells missing an addition cell missing has been studied to explain the logic signal strength effect physically. A QCA framework for the 3-input Ex-OR, 2:1 multiplexer, Fredkin, and Toffoli gate for the fault problem in which reliability analysis based on Hardware description language for QCA devices (HDLQ) is discussed and verified on the fault pattern look-up table.
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Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS... more
Digital circuits need improvement in computation speed, reducing circuit complexity and power consumption. Emerging Technology NML can be such an architecture at nano-scale and thus emerges as a viable alternative for the digital CMOS VLSI. This technology has the capability to compute the logic as well as storage into the same device, which points out that it great potential for emerging technology. Since Nano-magnetic, technology fast approaches its minimal feature size, high device density and operate at room temperature. NML based circuits synthesis has to opt for novel half subtraction and Binary-to-Gray architecture for achieving minimal complexity and high-speed performance. This manuscript pro-poses area efficient binary half-subtraction and Binary-to-Gray converter architecture. Circuits’ synthesize are performed by MagCAD tool and simulate by Modelsim simulator. The circuit’s performance are estimated over other existing designs. The proposed converter consume 73.73%, and 94.49% less area than the converter designed using QCA and CMOS technique respectively. This is a significant contribution to this paper. Simulation results of converter show that the critical path delay falls within 0.15 µs.
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Now researchers are moving toward emerging technologies to replace the conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of them for high-performance computing circuits. Ternary QCA is one of the finest research... more
Now researchers are moving toward emerging technologies to replace the conventional CMOS technology. Quantum-dot cellular automata (QCA) are one of them for high-performance computing circuits. Ternary QCA is one of the finest research areas in this domain for replacement of binary logic. In this paper, we proposed a new redundant adder architecture using Ternary QCA technology. Our proposed architecture has 233 numbers of cells with an area of 0.35 µm2. All the proposed ternary logic layouts are implemented in TQCA designer tool.
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Complete Lecture notes on Information Theory and Coding