Bahman Rashidi
Virginia Commonwealth University, Computer Science, Graduate Student
- Cloud Computing, Computer Engineering, Smartphones, Android Framework, Mobile Privacy, Linux kernel programming, and 10 moreDistributed System, Cloud Services, Virtualization, Information Security and Privacy, Privacy, Information Technology, Android Security, Computer Security, Computer Science, and Smartphoneedit
Description DroidCat logger is a software package developed to instrument Android applications and capture their log activities. The main merit of DroidCat is that it can instrument apps through real human-interaction, so we can get... more
Description DroidCat logger is a software package developed to instrument Android applications and capture their log activities. The main merit of DroidCat is that it can instrument apps through real human-interaction, so we can get behavior logs which highly assemble real world executing of Android apps. DroidCat Logger has been developed for XDroid project. You can find more details on the tool in the paper. Download Policy We are pleased to share this package, but in order to prevent any misuse, we ask you to send us an email to rashidib@vcu.edu. We will email you back the package. If you are in academia:
Research Interests: Computer Science, Information Security, Computer Engineering, Computer Security, Android Science, and 11 moreMobile application development, Behavior Analysis, Malware Analysis, Android, Smartphones, Development on Android platform, Android Development, Smartphone, Android Programming, Data Logger, and Smartphone Applications
The dataset contains 950 Android application logs from different malware categories. Applications are instrumented by human (real human-interaction) so the behavior logs highly assemble real world executing of Android apps. The dataset... more
The dataset contains 950 Android application logs from different malware categories. Applications are instrumented by human (real human-interaction) so the behavior logs highly assemble real world executing of Android apps. The dataset contains 440 malicious and 508 benign (normal) app logs. The logs have been captured for XDroid project. You can find more details on the dataset in the paper.
Research Interests: Computer Science, Computer Engineering, Android Science, Malware Analysis, Android, and 18 moreComputer Malware, Malware, Malware Detection, Smartphones, Development on Android platform, Malware Classification, Android Development, Malware Analysis and Detection, Malware Research, Mobile malwares, Malware Detection Techniques, Malware Reverse Engineering, Smartphone, Smartphone apps, Android Programming, Androids, Smartphone Applications, and Smartphone Security
Research Interests: Computer Science, Privacy, Recommender Systems, Bayesian, Security, and 13 moreBayesian Models, Bayesian Networks, Bayesian Analysis, Malware Analysis, Android, Malware, Bayesian Inference, Malware Detection, Smartphones, Android Development, Mobile malwares, Malware Reverse Engineering, and Smartphone
Research Interests: Stochastic Process, Computer Science, Privacy, Security, Markov Processes, and 13 moreMarkov Decision Process, Computer Security, Android Science, Behavior Analysis, Android, Malware, Markov chains, Hidden Markov Models, Malware Detection, hidden Markov model, Android Development, Mobile malwares, and Android Programming
—RecDroid is a smartphone permission management system which provides users with a fine-grained real-time app permission control and a recommendation system regarding whether to grant the permission or not based on expert users' responses... more
—RecDroid is a smartphone permission management system which provides users with a fine-grained real-time app permission control and a recommendation system regarding whether to grant the permission or not based on expert users' responses in the network. However, in such a system, malware owners may create multiple bot users to misguide the recommendation system by providing untruthful responses on the malicious app. Threshold-based detection method can detect malicious users which are dishonest on many apps, but it cannot detect malicious users that target on some specific apps. In this work, we present a clustering-based method called BotTracer to finding groups of bot users controlled by the same masters, which can be used to detect bot users with high reputation scores. The key part of the proposed method is to map the users into a graph based on their similarity and apply a clustering algorithm to group users together. We evaluate our method using a set of simulated users' profiles, including malicious users and regular ones. Our experimental results demonstrate high accuracy in terms of detecting malicious users. Finally, we discuss several clustering features and their impact on the clustering results.
Research Interests: Electrical Engineering, Computer Science, Information Security, Computer Engineering, Network Security, and 27 moreSecurity, Computer Security, Intrusion Detection Systems, Android Science, Malware Analysis, Android, Computer Malware, Malware, Intrusion Detection, Malware Detection, Smartphones, Development on Android platform, Cyber Security, Malware Classification, Android Development, Mobile malwares, Malware Detection Techniques, Malware Reverse Engineering, Smartphone, Smartphone apps, Android Programming, Malicious Website, Smartphone Applications, Malicious Node, Malware Forensics, Smartphone Security, and Malicious Software
RecDroid is a smartphone permission response recommendation system which utilizes the responses from expert users in the network to help inexperienced users. However, in such system, malicious users can mislead the recommendation system... more
RecDroid is a smartphone permission response recommendation system which utilizes the responses from expert users in the network to help inexperienced users. However, in such system, malicious users can mislead the recommendation system by providing untruthful responses. Although detection system can be deployed to detect the malicious users, and exclude them from recommendation system, there are still undetected malicious users that may cause damage to RecDroid. Therefore, relying on environment knowledge to detect the malicious users is not sufficient. In this work, we present a game-theoretic model to analyze the interaction (request/response) between RecDroid users and RecDroid system using a static Bayesian game formulation. In the game RecDroid system chooses the best response strategy to minimize its loss from malicious users. We analyze the game model and explain the Nash equilibrium in a static scenario under different conditions. Through the static game model we discuss the strategy that RecDroid can adopt to disincentivize attackers in the system, so that attackers are discouraged to perform malicious users attack. Finally, we discuss several game parameters and their impact on players' outcome.
Research Interests: Computer Science, Game Theory, Information Security, Computer Engineering, Privacy, and 40 moreGame Theory (Psychology), Bayesian, Network Security, Security, Security Studies, Decision And Game Theory, Video Game Theory, Evolutionary Game Theory, Computer Security, Behavioural Game Theory, Android Science, Information Security and Privacy, Bayesian Models, Role-playing Game Theory, Behavioral Game Theory, Algorithmic Game Theory, Bayesian Analysis, Android, Applications of Game Theory, Bayesian Inference, Applied Game Theory, Smartphones, Development on Android platform, Bayesian statistics, Cyber Security, Android Development, Tablets, smartphones, online media and consumption., Java and Androide Mobile Applicatation, Smartphone, Smartphone apps, Android Programming, Androids, Smartphone Applications, Business applications of game theory, The Coming Age of Androids, Electrical and Computer Engineering (ECE), Smartphone Security, Android security survay, Mobile Security Survay, and Smartphone Security Survay
In the recent years, Cloud Computing has been one of the top ten new technologies which provides various services such as software, platform and infrastructure for internet users. The Cloud Computing is a promising IT paradigm which... more
In the recent years, Cloud Computing has
been one of the top ten new technologies which provides
various services such as software, platform and
infrastructure for internet users. The Cloud Computing is
a promising IT paradigm which enables the Internet
evolution into a global market of collaborating services.
In order to provide better services for cloud customers,
cloud providers need services that are in cooperation
with other services. Therefore, Cloud Computing
semantic interoperability plays a key role in Cloud
Computing services. In this paper, we address
interoperability issues in Cloud Computing
environments. After a description of Cloud Computing
interoperability from different aspects and references,
we describe two architectures of cloud service
interoperability. Architecturally, we classify existing
interoperability challenges and we describe them.
Moreover, we use these aspects to discuss and compare
several interoperability approaches.
been one of the top ten new technologies which provides
various services such as software, platform and
infrastructure for internet users. The Cloud Computing is
a promising IT paradigm which enables the Internet
evolution into a global market of collaborating services.
In order to provide better services for cloud customers,
cloud providers need services that are in cooperation
with other services. Therefore, Cloud Computing
semantic interoperability plays a key role in Cloud
Computing services. In this paper, we address
interoperability issues in Cloud Computing
environments. After a description of Cloud Computing
interoperability from different aspects and references,
we describe two architectures of cloud service
interoperability. Architecturally, we classify existing
interoperability challenges and we describe them.
Moreover, we use these aspects to discuss and compare
several interoperability approaches.
Research Interests: Computer Science, Computer Engineering, Computer Networks, Clouds, Computer Security, and 22 moreInteroperability (E-learning), Cloud Computing, Software Interoperability, XML data interoperability, Interoperability, Semantic Interoperability, Cloud Computing Economy, Mobile Cloud Computing, Cloud, Cloud Computing Security, Cloud Security, Cloud Computing Introduction, Origin of Cloud Computing, Security in Cloud Computing, Information Systems Interoperability, Computer Network and Cloud Computing, Semantic Interoperability Framework, Web Mining and Cloud Computing, Cloud Computing and Virtualization, Web Services Interoperability, Interoperability Among Large Heterogeneous Systems, and Electrical and Computer Engineering (ECE)
This paper presents the methods to reduce dynamic power consumption of a digital Finite Imppulse Respanse (FIR) filter these mrthods include low power serial multiplier and serial adder, combinational booth multiplier, shift/add... more
This paper presents the methods to reduce dynamic
power consumption of a digital Finite Imppulse Respanse (FIR)
filter these mrthods include low power serial multiplier and
serial adder, combinational booth multiplier, shift/add
multipliers, folding transformation in linear pheas
architecture and applied to fir filters to power consumption
reduced thus reduce power consumption due to glitching is
also reduced. The minimum power achieved is 110mw in fir
filter based on shift/add multiplier in 100MHZ to 8taps and
8bits inputs and 8bits coefficions. The proposed FIR filters
were synthesized implemented using Xilinx ISE Virtex IV
power consumption of a digital Finite Imppulse Respanse (FIR)
filter these mrthods include low power serial multiplier and
serial adder, combinational booth multiplier, shift/add
multipliers, folding transformation in linear pheas
architecture and applied to fir filters to power consumption
reduced thus reduce power consumption due to glitching is
also reduced. The minimum power achieved is 110mw in fir
filter based on shift/add multiplier in 100MHZ to 8taps and
8bits inputs and 8bits coefficions. The proposed FIR filters
were synthesized implemented using Xilinx ISE Virtex IV
Research Interests: Electrical Engineering, Electronic Engineering, Power Electronics, Electronics, FPGA, and 21 moreElectronics & Telecommunication Engineering, Digital FPGA implementation, Electronics and communication, Electrical, Electric Power Systems, FPGA Architecture and CAD, FPGA and DSP, FPGA Architectures, Firma Digitale, Electronics Engineering, Managing Digital Firm, Mutiple processor scheduling on FPGA, FPGA-based systems design, FPGA design, Low Power Fir Digital Filter, Firma Digital, OFDM in FPGA, Xilinx FPGA,, FPGA based system design using VHDL, Electrical and Computer Engineering (ECE), and Xilinx
In last two decades continues increase of comput-ational power and recent advance in the web technology cause to provide large amounts of data. That needs large scale data processing mechanism to handle this volume of data. MapReduce is a... more
In last two decades continues increase of comput-ational power and recent advance in the
web technology cause to provide large amounts of data. That needs large scale data
processing mechanism to handle this volume of data. MapReduce is a programming model
for large scale distributed data processing in an efficient and transparent way. Due to its
excellent fault tolerance features, scalability and the ease of use. Currently, there are several
options for using MapReduce in cloud environments, such as using MapReduce as a service,
setting up one’s own MapReduce cluster on cloud instances, or using specialized cloud
MapReduce runtimes that take advantage of cloud infrastructure services. Cloud computing
has recently emerged as a new paradigm that provide computing infrastructure and large
scale data processing mechanism in the network. The cloud is on demand, scalable and high
availability so implement of MapReduce on the top of cloud services cause faster, scalable
and high available MapReduce framework for large scale data processing. In this paper we
explain how to implement MapReduce in the cloud and also have a comparison between
implementations of MapReduce on AzureCloud, Amazon Cloud and Hadoop at the end.
web technology cause to provide large amounts of data. That needs large scale data
processing mechanism to handle this volume of data. MapReduce is a programming model
for large scale distributed data processing in an efficient and transparent way. Due to its
excellent fault tolerance features, scalability and the ease of use. Currently, there are several
options for using MapReduce in cloud environments, such as using MapReduce as a service,
setting up one’s own MapReduce cluster on cloud instances, or using specialized cloud
MapReduce runtimes that take advantage of cloud infrastructure services. Cloud computing
has recently emerged as a new paradigm that provide computing infrastructure and large
scale data processing mechanism in the network. The cloud is on demand, scalable and high
availability so implement of MapReduce on the top of cloud services cause faster, scalable
and high available MapReduce framework for large scale data processing. In this paper we
explain how to implement MapReduce in the cloud and also have a comparison between
implementations of MapReduce on AzureCloud, Amazon Cloud and Hadoop at the end.
Research Interests: Computer Science, Computer Engineering, Computer Networks, Clouds, Cloud Computing, and 19 moreCloud Computing Economy, Mobile Cloud Computing, Mapreduce, Cloud, Cloud Computing Security, Cloud Security, Cloud Computing Introduction, Origin of Cloud Computing, Security in Cloud Computing, MapReduce in Volunteer Computing, Mapreduce Hadoop data Warehouse, MapReduce and Hadoop, Web Mining and Cloud Computing, Cloud Computing and Virtualization, Adaptive MapReduce In Hadoop, Electrical and Computer Engineering (ECE), Hadoop MapReduce, Improving Mapreduce Performance, and MapReduceFrameworks
This paper presents, complete step by step description design and implementation of a high speed technique for character segmentation of license plate based on thresholding algorithm. Because of vertical edges in the plate, fast Sobel... more
This paper presents, complete step by step
description design and implementation of a high speed
technique for character segmentation of license plate
based on thresholding algorithm. Because of vertical
edges in the plate, fast Sobel edge detection has been
used for extracting location of license plate, after stage
edge detection the image is segmented by thresholding
algorithm and the color of characters is changed to white
and the color of background is black. Then, boundary’s
pixels of license plate are scanned and their color is
changed to black pixels. Afterward the image is scanned
vertically and if the number of black pixels in a column
is equal to the width of plate or a little few, then the
pixels of that column is changed to white pixel, until
create white columns between characters, in continue
we change pixels around license plate to white pixels.
Finally characters are segmented cleanly. We test
proposed character segmentation algorithm for stage
recognition of number by code that we design. Results
of experimentation on different images demonstrate
ability of proposed algorithm. The accuracy of proposed
character segmentation is 99% and average time of
character segmentation is 15ms with thresholding
algorithm code and 0.7ms only segmentation character
code that is very small in comparison with other
algorithms.
description design and implementation of a high speed
technique for character segmentation of license plate
based on thresholding algorithm. Because of vertical
edges in the plate, fast Sobel edge detection has been
used for extracting location of license plate, after stage
edge detection the image is segmented by thresholding
algorithm and the color of characters is changed to white
and the color of background is black. Then, boundary’s
pixels of license plate are scanned and their color is
changed to black pixels. Afterward the image is scanned
vertically and if the number of black pixels in a column
is equal to the width of plate or a little few, then the
pixels of that column is changed to white pixel, until
create white columns between characters, in continue
we change pixels around license plate to white pixels.
Finally characters are segmented cleanly. We test
proposed character segmentation algorithm for stage
recognition of number by code that we design. Results
of experimentation on different images demonstrate
ability of proposed algorithm. The accuracy of proposed
character segmentation is 99% and average time of
character segmentation is 15ms with thresholding
algorithm code and 0.7ms only segmentation character
code that is very small in comparison with other
algorithms.
Research Interests: Electrical Engineering, Electronic Engineering, Computer Science, Computer Architecture, Computer Graphics, and 25 moreComputer Vision, Image Processing, Computer Engineering, Power Electronics, Electronics, Medical Image Processing, Electronics & Telecommunication Engineering, Image and Video Compression, Image Analysis, Biomedical signal and image processing, Electronics and communication, Electrical, Image segmentation, Digital Image Processing, Signal and Image Processing, Character Segmentation, Engineering and Computer Science, Electronics Engineering, Computer Science And Engineering, Computer Systems Engineering, Computer Science Engineering, Handwritten Character Segmentation, Electrical and Computer Engineering (ECE), Computer Science and Engineering, and Electrical and Computer Engineering
This paper presents, a low power 128-bit Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed architecture for encryption of audio signals. An asynchronous system is defined as one where the transfers of... more
This paper presents, a low power 128-bit
Advanced Encryption Standard (AES) algorithm based
on a novel asynchronous self-timed architecture for
encryption of audio signals. An asynchronous system is
defined as one where the transfers of information
between combinatorial blocks without a global clock
signal. The self-timed architectures are asynchronous
circuits which perform their function based on local
synchronization signals called hand shake, independently
from the other modules. This new architecture reduced
spikes on current consumption and only parts with valid
data are working, and also this design does not need any
clock pulse. A combinational logic based Rijndael S-Box
implementation for the Substitution Byte transformation
in AES is proposed, its low area occupancy and high
throughput therefore proposed digital design leads to
reduction in power consumption. Mix-columns
transformation is implemented only based on multiplyby-2
and multiply-by-3 modules with combinational logic.
The proposed novel asynchronous self-timed AES
algorithm is modeled and verified using FPGA and
simulation results from encryption of sound signals is
presented, until original characteristics are preserved
anymore and have been successfully synthesized and
implemented using Xilinx ISE V7.1 and Virtex IV FPGA
to target device Xc4vf100. The achieved power
consumption is 283 mW in clock frequency of 100 MHz
Advanced Encryption Standard (AES) algorithm based
on a novel asynchronous self-timed architecture for
encryption of audio signals. An asynchronous system is
defined as one where the transfers of information
between combinatorial blocks without a global clock
signal. The self-timed architectures are asynchronous
circuits which perform their function based on local
synchronization signals called hand shake, independently
from the other modules. This new architecture reduced
spikes on current consumption and only parts with valid
data are working, and also this design does not need any
clock pulse. A combinational logic based Rijndael S-Box
implementation for the Substitution Byte transformation
in AES is proposed, its low area occupancy and high
throughput therefore proposed digital design leads to
reduction in power consumption. Mix-columns
transformation is implemented only based on multiplyby-2
and multiply-by-3 modules with combinational logic.
The proposed novel asynchronous self-timed AES
algorithm is modeled and verified using FPGA and
simulation results from encryption of sound signals is
presented, until original characteristics are preserved
anymore and have been successfully synthesized and
implemented using Xilinx ISE V7.1 and Virtex IV FPGA
to target device Xc4vf100. The achieved power
consumption is 283 mW in clock frequency of 100 MHz
Research Interests: Electrical Engineering, Electronic Engineering, Power Electronics, Electronics, FPGA, and 15 moreElectronics & Telecommunication Engineering, Digital FPGA implementation, Electronics and communication, Electrical, Electric Power Systems, FPGA Architecture and CAD, FPGA and DSP, FPGA Architectures, Electronics Engineering, FPGA-based systems design, FPGA design, Low power Design and Power Estimation. XIlinx FPGA Based Application Development and Implementations, OFDM in FPGA, FPGA based system design using VHDL, and Electrical and Computer Engineering (ECE)
In this paper, presents an optimized combinational logic based Rijndael S-Box implementation for the SubByte transformation(S-box) in the Advanced Encryption Standard (AES) algorithm on FPGA. S-box dominated the hardware complexity of the... more
In this paper, presents an optimized
combinational logic based Rijndael S-Box
implementation for the SubByte transformation(S-box) in
the Advanced Encryption Standard (AES) algorithm on
FPGA. S-box dominated the hardware complexity of the
AES cryptographic module thus we implement its
mathematic equations based on optimized and
combinational logic circuits until dynamic power
consumption reduced. The complete data path of the Sbox
algorithm is simulated as a net list of AND, OR,
NOT and XOR logic gates, also for increase in speed and
maximum operation frequency used 4-stage pipeline in
proposed method. The proposed implemented
combinational logic based S-box have been successfully
synthesized and implemented using Xilinx ISE V7.1 and
Virtex IV FPGA to target device Xc4vf100. Power is
analized using Xilinx XPower analyzer and achieved
power consumption is 29 mW in clock frequency of 100
MHz. The results from the Place and Route report
indicate that maximum clock frequency is 209.617 MHz.
combinational logic based Rijndael S-Box
implementation for the SubByte transformation(S-box) in
the Advanced Encryption Standard (AES) algorithm on
FPGA. S-box dominated the hardware complexity of the
AES cryptographic module thus we implement its
mathematic equations based on optimized and
combinational logic circuits until dynamic power
consumption reduced. The complete data path of the Sbox
algorithm is simulated as a net list of AND, OR,
NOT and XOR logic gates, also for increase in speed and
maximum operation frequency used 4-stage pipeline in
proposed method. The proposed implemented
combinational logic based S-box have been successfully
synthesized and implemented using Xilinx ISE V7.1 and
Virtex IV FPGA to target device Xc4vf100. Power is
analized using Xilinx XPower analyzer and achieved
power consumption is 29 mW in clock frequency of 100
MHz. The results from the Place and Route report
indicate that maximum clock frequency is 209.617 MHz.