Chapter 9 shows that the digitization of a ΣΔ modulator can be done at different abstraction leve... more Chapter 9 shows that the digitization of a ΣΔ modulator can be done at different abstraction levels, which are system/application level, analog IP architecture level and circuit/layout level. In this section ΣΔ modulator implementations suited for highly digitized receiver systems, an implementation that is digitized at modulator architecture level, and a modulator that is designed using the digital design methodology will be shown. At the end of Chap. 9 the implemented ΣΔ modulators will be judged on the quality indicators of Chap. 2 and the FOMs of Chap. 8.
2012 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT), 2012
This paper describes a fully integrated power amplifier working at 60GHz band and implemented in ... more This paper describes a fully integrated power amplifier working at 60GHz band and implemented in CMOS 65nm technology. The ring topology of a distributed active transformer (DAT) is applied to realize efficient power combination and impedance transformation simultaneously. The design consists of the transformer, active stages, and input power divider, and the matching networks between the components are implemented to form the complete system. The power amplifier achieves a simulated 21.36 dBm output power at 1 dB compression, with 1dB bandwidth of 12.5 GHz. The power added efficiency of total system is 4.56% and the transducer gain is 4.95 dB.
Nanoscale devices can be built from single electron tunnel junctions. The typical size of such a ... more Nanoscale devices can be built from single electron tunnel junctions. The typical size of such a junction is a few nanometers. Because of these small sizes, the device is more sensitive for process variatons, temperature fluctuations, and load capacitances. These and environmental vari- ations result in transfer errors. A possible solu- tion for these errors is the application of neural
Millimeter wave layout and measurements pose serious challenges during the IC design cycle. There... more Millimeter wave layout and measurements pose serious challenges during the IC design cycle. Therefore, this chapter is dedicated to discuss the various issues encountered and proposes solutions for them. The first part of the chapter elaborates the impact of parasitics, layout mismatch, substrate losses and shielding whereas the second part discusses the measurement issues like calibration, de-embedding, stability and repeatability.
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016
This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM ba... more This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
This chapter gives a detailed description of analogue and mixed-signal circuit design, focusing i... more This chapter gives a detailed description of analogue and mixed-signal circuit design, focusing in particular on the S2S printed organic complementary technology. The design and characterisation of several building blocks based on different architectures are shown. After discussing simple differential OTAs, a mismatch-free comparator exploiting offset-cancellation techniques is demonstrated. This circuit is able to resolve differential input voltages as small as 50 mV for a Vdd of 40 V: a remarkable sensitivity for printed electronics. A printed DAC, the first ever demonstrated, is also shown. This DAC, based on a “R-2R” resistive network, achieves a maximum INL of 0.04 LSB at a resolution level of 4 bits. In addition, the HF behaviour of printed diode-connected OTFTs is studied and a four-stage rectifier is presented.
Analog Integrated Circuits and Signal Processing, 2000
According to recent studies, the basic technologies presently adopted by the semiconductor indust... more According to recent studies, the basic technologies presently adopted by the semiconductor industry for memory and processor fabrication should attain limits imposed by the laws of physics around the year 2010. Nanoscale sized devices like single-electron transistors appear as a highly promising option to replace conventional devices by that time. In this study, considerations about the realization of a GSI
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
ABSTRACT This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal ... more ABSTRACT This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal monitoring applications. The noise specification of the IA is made adaptive to the peak-peak value of the fetal electrocardiography (fECG) signal, which varies for different gestational age and measurement settings. Contrary to the currently available point solution IAs, the proposed IA is scalable for a noise range from 30nV/VHz to 250nV/VHz while consuming 15μW to 1μW respectively. A new IA architecture is proposed to achieve a better noise efficiency factor (NEF), while allowing noise scalability. The IA is designed in TSMC 0.18μm CMOS process. Simulation results show that the IA achieves a NEF of 3.4 to 5.5 over the noise scalable range, a CMRR of 100dB, and an input impedance (Zin) of 1GO.
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively weara... more Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.
ABSTRACT This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifie... more ABSTRACT This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifier in 65nm CMOS technology. The rectenna is often the bottleneck in realizing a fully-integrated monolithic wireless sensor tag. In this paper, problems of the mm-wave rectifier are discussed, and the self-threshold voltage modulation method is proposed for better sensitivity and efficiency. Based on this discussion, the design of a 60 GHz rectenna is provided. The designed on-chip antenna has 2 dBi gain at 60 GHz. The designed rectifier reaches 4.4% efficiency with 7 dBm input power with a 1.5 kΩ load in simulation.
Chapter 9 shows that the digitization of a ΣΔ modulator can be done at different abstraction leve... more Chapter 9 shows that the digitization of a ΣΔ modulator can be done at different abstraction levels, which are system/application level, analog IP architecture level and circuit/layout level. In this section ΣΔ modulator implementations suited for highly digitized receiver systems, an implementation that is digitized at modulator architecture level, and a modulator that is designed using the digital design methodology will be shown. At the end of Chap. 9 the implemented ΣΔ modulators will be judged on the quality indicators of Chap. 2 and the FOMs of Chap. 8.
2012 19th IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT), 2012
This paper describes a fully integrated power amplifier working at 60GHz band and implemented in ... more This paper describes a fully integrated power amplifier working at 60GHz band and implemented in CMOS 65nm technology. The ring topology of a distributed active transformer (DAT) is applied to realize efficient power combination and impedance transformation simultaneously. The design consists of the transformer, active stages, and input power divider, and the matching networks between the components are implemented to form the complete system. The power amplifier achieves a simulated 21.36 dBm output power at 1 dB compression, with 1dB bandwidth of 12.5 GHz. The power added efficiency of total system is 4.56% and the transducer gain is 4.95 dB.
Nanoscale devices can be built from single electron tunnel junctions. The typical size of such a ... more Nanoscale devices can be built from single electron tunnel junctions. The typical size of such a junction is a few nanometers. Because of these small sizes, the device is more sensitive for process variatons, temperature fluctuations, and load capacitances. These and environmental vari- ations result in transfer errors. A possible solu- tion for these errors is the application of neural
Millimeter wave layout and measurements pose serious challenges during the IC design cycle. There... more Millimeter wave layout and measurements pose serious challenges during the IC design cycle. Therefore, this chapter is dedicated to discuss the various issues encountered and proposes solutions for them. The first part of the chapter elaborates the impact of parasitics, layout mismatch, substrate losses and shielding whereas the second part discusses the measurement issues like calibration, de-embedding, stability and repeatability.
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016
This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM ba... more This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
This chapter gives a detailed description of analogue and mixed-signal circuit design, focusing i... more This chapter gives a detailed description of analogue and mixed-signal circuit design, focusing in particular on the S2S printed organic complementary technology. The design and characterisation of several building blocks based on different architectures are shown. After discussing simple differential OTAs, a mismatch-free comparator exploiting offset-cancellation techniques is demonstrated. This circuit is able to resolve differential input voltages as small as 50 mV for a Vdd of 40 V: a remarkable sensitivity for printed electronics. A printed DAC, the first ever demonstrated, is also shown. This DAC, based on a “R-2R” resistive network, achieves a maximum INL of 0.04 LSB at a resolution level of 4 bits. In addition, the HF behaviour of printed diode-connected OTFTs is studied and a four-stage rectifier is presented.
Analog Integrated Circuits and Signal Processing, 2000
According to recent studies, the basic technologies presently adopted by the semiconductor indust... more According to recent studies, the basic technologies presently adopted by the semiconductor industry for memory and processor fabrication should attain limits imposed by the laws of physics around the year 2010. Nanoscale sized devices like single-electron transistors appear as a highly promising option to replace conventional devices by that time. In this study, considerations about the realization of a GSI
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
ABSTRACT This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal ... more ABSTRACT This paper proposes a low-power noise scalable instrumentation amplifier (IA) for fetal monitoring applications. The noise specification of the IA is made adaptive to the peak-peak value of the fetal electrocardiography (fECG) signal, which varies for different gestational age and measurement settings. Contrary to the currently available point solution IAs, the proposed IA is scalable for a noise range from 30nV/VHz to 250nV/VHz while consuming 15μW to 1μW respectively. A new IA architecture is proposed to achieve a better noise efficiency factor (NEF), while allowing noise scalability. The IA is designed in TSMC 0.18μm CMOS process. Simulation results show that the IA achieves a NEF of 3.4 to 5.5 over the noise scalable range, a CMRR of 100dB, and an input impedance (Zin) of 1GO.
2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively weara... more Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester attached to a running person delivers only 7.4nW [2]. While several low-power signal acquisition systems have been proposed [3-5], their consumption is still in the 20-to-1000nW range. Circuits aiming at low absolute power often result in low power-efficiency (due to overhead), high PVT sensitivity and poor reliability (due to the use of simplistic circuitry). This work presents a fully-integrated signal acquisition IC with six-fold lower power consumption than prior art, which provides state-of-the-art power-efficiency and ensures enough circuit reliability, precision and bandwidth to enable practical applications.
ABSTRACT This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifie... more ABSTRACT This paper presents the design of a 60-GHz rectenna with an on-chip antenna and rectifier in 65nm CMOS technology. The rectenna is often the bottleneck in realizing a fully-integrated monolithic wireless sensor tag. In this paper, problems of the mm-wave rectifier are discussed, and the self-threshold voltage modulation method is proposed for better sensitivity and efficiency. Based on this discussion, the design of a 60 GHz rectenna is provided. The designed on-chip antenna has 2 dBi gain at 60 GHz. The designed rectifier reaches 4.4% efficiency with 7 dBm input power with a 1.5 kΩ load in simulation.
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