AbstractÐThis paper presents an analysis of radix representations of elements from general rings;... more AbstractÐThis paper presents an analysis of radix representations of elements from general rings; in particular, we study the questions of redundancy and completeness in such representations. Mappings into radix representations, as well as conversions between such, are discussed, in particular where the target system is redundant. Results are shown valid for normed rings containing only a finite number of elements with a bounded distance from zero, essentially assuring that the ring is ªdiscrete.º With only brief references to the more usual representations of integers, the emphasis is on various complex number systems, including the ªclassicalº complex number systems for the Gaussian integers, as well as the Eisenstein integers, concluding with a summary on properties of some low-radix representations of such systems. Index TermsÐRadix representation of rings, integer and computer radix number systems, redundancy, number system conversion, computer arithmetic. 1
this paper. By introducing an extratermination symbol, which signals that an operand was merely t... more this paper. By introducing an extratermination symbol, which signals that an operand was merely terminated due toits length exceeding some bound, operands can be kept as intervals, representingan imprecise operand. Operands terminated in the ordinary way can be taken torepresent exact numbers.The cube modeling a function of two variables, can be generalized to a hypercube modeling a poly-homographic function of
This paper presents a floating point addition algorithm and adder pipeline design employing a pac... more This paper presents a floating point addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply pipelined oating point pipelines. The addition and rounding algorithms employ a four stage execution phase pipeline with each stage suitable for implementation in a short clock period, assuming about fteen logic levels per cycle. The first two cycles are related to addition proper and are the focus of this paper. The last two cycles perform the rounding and have been covered in a paper by Nielsen and Matula [8]. The addition algorithm accepts one operand in a standard binary oating point format at the start of cycle one. The second operand is represented in the packet forwarding oating point format, namely, it is divided into four parts: the sign bit, the exponent string, the principal part of the significand, and the carry-round packet....
The paper presents the foundations for a packet forwarding floating point format and the design o... more The paper presents the foundations for a packet forwarding floating point format and the design of a rounder ensuring compatibility between packet forwarding format and the standard binary IEEE 754 floating point format. The packet forwarding format and related addition and multiplication algorithms described in this series propose a new ALU pipeline paradigm for handling data hazards in pipelined floating point operations. The execution phases for the adder and multiplier packet forwarding pipelines are illustrated by a proposed implementation having four stages. The latter two stages in each pipeline employ the rounder described herein. The stages of the execution phase are intended to map to logic designs, with only some fifteen logic levels per stage allowing stages to be mapped to reasonably short cycles. The packet forwarding format provides for input and output in packet format with only two cycle effective latency between cooperating adder and multiplier pipelines. The desig...
AbstractÐThis paper presents an analysis of radix representations of elements from general rings;... more AbstractÐThis paper presents an analysis of radix representations of elements from general rings; in particular, we study the questions of redundancy and completeness in such representations. Mappings into radix representations, as well as conversions between such, are discussed, in particular where the target system is redundant. Results are shown valid for normed rings containing only a finite number of elements with a bounded distance from zero, essentially assuring that the ring is ªdiscrete.º With only brief references to the more usual representations of integers, the emphasis is on various complex number systems, including the ªclassicalº complex number systems for the Gaussian integers, as well as the Eisenstein integers, concluding with a summary on properties of some low-radix representations of such systems. Index TermsÐRadix representation of rings, integer and computer radix number systems, redundancy, number system conversion, computer arithmetic. 1
this paper. By introducing an extratermination symbol, which signals that an operand was merely t... more this paper. By introducing an extratermination symbol, which signals that an operand was merely terminated due toits length exceeding some bound, operands can be kept as intervals, representingan imprecise operand. Operands terminated in the ordinary way can be taken torepresent exact numbers.The cube modeling a function of two variables, can be generalized to a hypercube modeling a poly-homographic function of
This paper presents a floating point addition algorithm and adder pipeline design employing a pac... more This paper presents a floating point addition algorithm and adder pipeline design employing a packet forwarding pipeline paradigm. The packet forwarding format and the proposed algorithms constitute a new paradigm for handling data hazards in deeply pipelined oating point pipelines. The addition and rounding algorithms employ a four stage execution phase pipeline with each stage suitable for implementation in a short clock period, assuming about fteen logic levels per cycle. The first two cycles are related to addition proper and are the focus of this paper. The last two cycles perform the rounding and have been covered in a paper by Nielsen and Matula [8]. The addition algorithm accepts one operand in a standard binary oating point format at the start of cycle one. The second operand is represented in the packet forwarding oating point format, namely, it is divided into four parts: the sign bit, the exponent string, the principal part of the significand, and the carry-round packet....
The paper presents the foundations for a packet forwarding floating point format and the design o... more The paper presents the foundations for a packet forwarding floating point format and the design of a rounder ensuring compatibility between packet forwarding format and the standard binary IEEE 754 floating point format. The packet forwarding format and related addition and multiplication algorithms described in this series propose a new ALU pipeline paradigm for handling data hazards in pipelined floating point operations. The execution phases for the adder and multiplier packet forwarding pipelines are illustrated by a proposed implementation having four stages. The latter two stages in each pipeline employ the rounder described herein. The stages of the execution phase are intended to map to logic designs, with only some fifteen logic levels per stage allowing stages to be mapped to reasonably short cycles. The packet forwarding format provides for input and output in packet format with only two cycle effective latency between cooperating adder and multiplier pipelines. The desig...
Uploads
Papers