Tao Chuan Lim

For the first time, the high frequency (HF) performance of an ultra-thinned body (UTB) fully depleted silicon-on-insulator (FDSOI) incorporating TiN/HfO2 gate stack is reported. Full small signal equivalent parameters of UTB-FDSOI are extracted and analysed in detailed. It is revealed that UTB-FDSOI with longer unit width WU (same total width WTOT) results in slightly higher gm that leads to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high-K dielectric and silicon, the measured transition frequency (fT) still corresponds well to that predicted from the ITRS roadmap. Optimising the gate stack for low RG is crucial as huge RG in the current technology is the key parameter responsible for the low fMAX obtained. This work can also be considered as the first ever experimental device measured suitable to be used for the Low STand-by Power (LSTP)-based RF/mobile application.

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic CV/I delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent ION/IOFF characteristics (NMOS: 2.33 mA/mum at 27 pA/mum and PMOS: 1.52 mA/mum at 38 pA/mum). A gate capacitance C gg reduction of 32% is measured, thanks to S-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain A VI( = gm/g ds) is improved by 92%.

Abstract—In this letter, we propose a design methodology to enhance the High Frequency noise performance of the tradi-tional CMOS technology via channel engineering. We show that the intrinsic noise correlation coefficient (C) of the conventional CMOS (∼0.4 or lower) limits ...