Unmanned Aerial Vehicles (UAVs) can be used for close range mapping. In engineering survey works,... more Unmanned Aerial Vehicles (UAVs) can be used for close range mapping. In engineering survey works, the conventional survey involves huge cost, labour, and time. Low-cost UAVs are very practical in providing reliable information for many applications such as road design, bridges, Land surveys etc. UAVs can provide the output that meets the accuracy of engineering surveys and policies, especially for small-scale mapping. UAVs are also a competitive technology which is stable and rapidly developing, same as other surveying technologies. This study investigates the performance of multirotor UAV for Sona College campus. This study involves four phases which consist of preliminary study, data collection, data processing, and analysis. This study focuses on the UAV as a tool to capture data of the whole college campus from a certain altitude. The analysis includes UAV flight planning, image acquisition, and accuracy assessment of College campus with recent technological advancements, the use of drones also called unmanned aerial vehicles (UAVs) is continuously increasing in various fields. Many industries are embracing the rapidly improving scientific tools and introducing smart solutions to solve real-world problems. It can be concluded that UAVs can be used to provide all required surveying data of Sona College Campus with reliable accuracy.
The advancement in digital signal processing with its various other applications made digital mul... more The advancement in digital signal processing with its various other applications made digital multipliers to play major role in technology. Many researchers are working to design multipliers which offer either of the following design targets – high speed, low power consumption and less area. Furthermore, the negative bias temperature instability effect occurs when a pMOS transistor is under –ve bias (Vgs = −Vdd), increasing the Vt (threshold voltage) of the pMOS transistor, and declinement in multiplier speed. Similarly, +ve bias temperature instability, occurs when an nMOS transistor is under positive bias. Both the effects directly hinder the multiplier speed by degrading transistor speed, if this problem occurs for long time then the system may fail due to timing violations. To overcome the timing violations, Variable latency technique is used. Therefore, it is important to design efficient high-performance multipliers. In this paper, we propose a high speed multiplier design using Modified booth multiplier algorithm. The multiplier designed using booth algorithm have two 16-bit input and 32-bit output and is able to provide higher throughput through the variable latency and can adjust the AHL circuit with help of Razor flip flop to mitigate performance degradation that is due to the aging effect. The design and implementation of Efficient Multiplier Design using Advanced Booth Algorithm and Razor Flip Flop. The proposed architecture is quite different from the Conventional method of multiplier like row/column bypass multiplier. The proposed architecture is simulated and implemented on XilinxISE 14.2
Unmanned Aerial Vehicles (UAVs) can be used for close range mapping. In engineering survey works,... more Unmanned Aerial Vehicles (UAVs) can be used for close range mapping. In engineering survey works, the conventional survey involves huge cost, labour, and time. Low-cost UAVs are very practical in providing reliable information for many applications such as road design, bridges, Land surveys etc. UAVs can provide the output that meets the accuracy of engineering surveys and policies, especially for small-scale mapping. UAVs are also a competitive technology which is stable and rapidly developing, same as other surveying technologies. This study investigates the performance of multirotor UAV for Sona College campus. This study involves four phases which consist of preliminary study, data collection, data processing, and analysis. This study focuses on the UAV as a tool to capture data of the whole college campus from a certain altitude. The analysis includes UAV flight planning, image acquisition, and accuracy assessment of College campus with recent technological advancements, the use of drones also called unmanned aerial vehicles (UAVs) is continuously increasing in various fields. Many industries are embracing the rapidly improving scientific tools and introducing smart solutions to solve real-world problems. It can be concluded that UAVs can be used to provide all required surveying data of Sona College Campus with reliable accuracy.
The advancement in digital signal processing with its various other applications made digital mul... more The advancement in digital signal processing with its various other applications made digital multipliers to play major role in technology. Many researchers are working to design multipliers which offer either of the following design targets – high speed, low power consumption and less area. Furthermore, the negative bias temperature instability effect occurs when a pMOS transistor is under –ve bias (Vgs = −Vdd), increasing the Vt (threshold voltage) of the pMOS transistor, and declinement in multiplier speed. Similarly, +ve bias temperature instability, occurs when an nMOS transistor is under positive bias. Both the effects directly hinder the multiplier speed by degrading transistor speed, if this problem occurs for long time then the system may fail due to timing violations. To overcome the timing violations, Variable latency technique is used. Therefore, it is important to design efficient high-performance multipliers. In this paper, we propose a high speed multiplier design using Modified booth multiplier algorithm. The multiplier designed using booth algorithm have two 16-bit input and 32-bit output and is able to provide higher throughput through the variable latency and can adjust the AHL circuit with help of Razor flip flop to mitigate performance degradation that is due to the aging effect. The design and implementation of Efficient Multiplier Design using Advanced Booth Algorithm and Razor Flip Flop. The proposed architecture is quite different from the Conventional method of multiplier like row/column bypass multiplier. The proposed architecture is simulated and implemented on XilinxISE 14.2
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In this paper, we propose a high speed multiplier design using Modified booth multiplier algorithm. The multiplier designed using booth algorithm have two 16-bit input and 32-bit output and is able to provide higher throughput through the variable latency and can adjust the AHL circuit with help of Razor flip flop to mitigate performance degradation that is due to the aging effect. The design and implementation of Efficient Multiplier Design using Advanced Booth Algorithm and Razor Flip Flop. The proposed architecture is quite different from the Conventional method of multiplier like row/column bypass multiplier. The proposed architecture is simulated and implemented on XilinxISE 14.2
In this paper, we propose a high speed multiplier design using Modified booth multiplier algorithm. The multiplier designed using booth algorithm have two 16-bit input and 32-bit output and is able to provide higher throughput through the variable latency and can adjust the AHL circuit with help of Razor flip flop to mitigate performance degradation that is due to the aging effect. The design and implementation of Efficient Multiplier Design using Advanced Booth Algorithm and Razor Flip Flop. The proposed architecture is quite different from the Conventional method of multiplier like row/column bypass multiplier. The proposed architecture is simulated and implemented on XilinxISE 14.2