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Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by assigning the frequently-accessed data to the low levels of memory hierarchy. Within a given level of hierarchy, energy... more
Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by assigning the frequently-accessed data to the low levels of memory hierarchy. Within a given level of hierarchy, energy and access times can be further reduced by memory banking. This paper addresses the problem of banking optimization, presenting a dynamic programming approach that takes into account all three major design objectives - energy consumption, performance, and die area, letting the designers decide on their relative importance for a specific project. The time complexity is independent of the size of the storage access trace and of the memory size - a significant advantage in terms of computation speed when these two parameters are large.
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ABSTRACT Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by exploiting the non-uniformity of memory accesses and assigning the frequently-accessed data to the low levels... more
ABSTRACT Hierarchical memory organizations are used in embedded systems to reduce energy consumption and improve performance by exploiting the non-uniformity of memory accesses and assigning the frequently-accessed data to the low levels of memory hierarchy. Moreover, within a given level, energy can be further reduced and performance further enhanced by memory partitioning - whose principle is to divide the address space in several smaller blocks and to map these blocks to physical memory banks. Scratch-pad memories (SPMs) offer a good compromise - as on-chip storage in embedded systems - when taking into account performance, energy consumption, and die area. This paper addresses the problem of optimizing the partitioning of SPMs. Different from previous techniques, the cost function takes into account all the three major design objectives - energy consumption, performance, and die area, letting the designers decide on their relative importance for a specific project. The proposed approach proved to be computationally fast and very efficient when tested for several data-intensive applications, whose behavioral specifications contain multidimensional arrays as main data structures.
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ABSTRACT This paper presents an energy-aware electronic design automation (EDA) methodology for the system-level exploration of hierarchical storage organizations, focusing mainly on data-intensive signal processing applications. Starting... more
ABSTRACT This paper presents an energy-aware electronic design automation (EDA) methodology for the system-level exploration of hierarchical storage organizations, focusing mainly on data-intensive signal processing applications. Starting from the high-level behavioral specification of a given application, several memory management tasks are addressed in a common algebraic framework, using data-dependence analysis techniques similar to those used in modern compilers. Within this memory management software system, the designer can explore different algorithmic specifications functionally equivalent, by computing their minimum storage requirements. The system can perform an exploration based on energy consumption of signal assignments to the off- and on-chip memory layers, followed by a storage-efficient mapping of signals to the physical memories. The last phase of the methodology is an exploration approach for energy-aware banking of the on-chip memory, which takes into account both the static and dynamic energy consumption.
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ABSTRACT Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects - namely power consumption, performance, and chip... more
ABSTRACT Many signal processing systems, particularly in the multimedia and telecommunication domains, are synthesized to execute data-intensive applications: their cost related aspects - namely power consumption, performance, and chip area - are heavily influenced, if not dominated, by the data transfer and storage aspects. In such applications, hierarchical memory organizations reduce energy consumption by exploiting the nonuniformity of memory accesses and assigning the frequentlyaccessed data to low levels of the hierarchy. Moreover, within a given level, power can be reduced by memory partitioning - whose principle is to divide the address space in several smaller blocks, and to map these blocks to physical memory banks. This paper addresses the problem of energy-aware banking of on-chip memories for data-intensive applications, proposing a technique that is guided by the intensity of memory accesses within the array space of signals.
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The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The... more
The gate arrays option in manufacturing ASIC CMOS is conditioned by the possibility of satisfying small orders requirements of small- and medium-sized electronic equipment manufacturing companies, in a large variety of circuits. The authors present contributions in optimizing critical processes for an n-well CMOS polysilicon gate arrays technology. Technological achievements were proved by measurements on the test devices but mainly