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Navlakha et al., 2018 - Google Patents

Performance assessment of TFET architectures as 1T-DRAM

Navlakha et al., 2018

Document ID
9833590740821758852
Author
Navlakha N
Ansari M
Lin J
Kranti A
Publication year
Publication venue
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

External Links

Snippet

An assessment of Tunnel FET (TFET) architectures for capacitorless dynamic memory applications is presented through composite metrics to balance various trade-offs while regulating hole distribution to determine sense margin, retention time and current ratio. The …
Continue reading at ieeexplore.ieee.org (other versions)

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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