Wei, 2001 - Google Patents
Energy-efficient I/O interface design with adaptive power-supply regulationWei, 2001
View PDF- Document ID
- 960189894839091635
- Author
- Wei G
- Publication year
External Links
Snippet
The demand for high-bandwidth and low-power I/O interfaces for intra-chip communication motivates this work. Aggressive CMOS scaling has enabled higher performance and integration at the expense of higher power dissipation and design complexity. This work …
- 230000003044 adaptive 0 title description 26
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; Arrangements for supplying electrical power along data transmission lines
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10211841B2 (en) | Method and apparatus for source-synchronous signaling | |
Kim et al. | Adaptive supply serial links with sub-1-V operation and per-pin clock recovery | |
US8680903B2 (en) | Locked loop circuit with clock hold function | |
Sidiropoulos et al. | A semidigital dual delay-locked loop | |
US7046056B2 (en) | System with dual rail regulated locked loop | |
Wong et al. | A 27-mW 3.6-gb/s I/O transceiver | |
US8183899B2 (en) | Semiconductor integrated circuit and control method for clock signal synchronization | |
Wei et al. | A variable-frequency parallel I/O interface with adaptive power-supply regulation | |
EP1250638B1 (en) | System and method for compensating for supply voltage induced signal delay mismatches | |
US7135903B2 (en) | Phase jumping locked loop circuit | |
Gangasani et al. | A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology | |
US6922091B2 (en) | Locked loop circuit with clock hold function | |
Loke et al. | An 8.0-Gb/s HyperTransport transceiver for 32-nm SOI-CMOS server processors | |
Wei | Energy-efficient I/O interface design with adaptive power-supply regulation | |
Kim | Design of CMOS adaptive-supply serial links | |
Wei et al. | Energy-efficient design of high-speed links | |
US20070116164A1 (en) | Clock alignment detection from single reference | |
Kwon et al. | An adaptive-bandwidth referenceless CDR with small-area coarse and fine frequency detectors | |
EP1495544B1 (en) | System with phase jumping locked loop circuit | |
Choi | Design of energy-efficient high-speed wireline transceiver | |
Rhee et al. | A continuously tunable LC-VCO PLL with bandwidth linearization techniques for PCI express Gen2 applications | |
Wu | Low jitter design techniques for monolithic CMOS phase-locked and delay-locked systems |