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Held et al., 2017 - Google Patents

Fast prefix adders for non-uniform input arrival times

Held et al., 2017

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Document ID
9135025921063389822
Author
Held S
Spirkl S
Publication year
Publication venue
Algorithmica

External Links

Snippet

We consider the problem of constructing fast and small parallel prefix adders for non-uniform input arrival times. In modern computer chips, adders with up to hundreds of inputs occur frequently, and they are often embedded into more complex circuits, eg multipliers, leading …
Continue reading at arxiv.org (PDF) (other versions)

Classifications

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    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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