Krikelis, 1991 - Google Patents
A novel massively associative processing architecture for the implementation of artificial neural networksKrikelis, 1991
- Document ID
- 9110835895374429461
- Author
- Krikelis A
- Publication year
- Publication venue
- [Proceedings] ICASSP 91: 1991 International Conference on Acoustics, Speech, and Signal Processing
External Links
Snippet
The author presents the ASP (associative string processor) a massively parallel, programmable, fault-tolerant architecture, which can efficiently support low-MIMD/high-SIMD and other parallel computation paradigms by providing comprehensive cover of both …
- 230000001537 neural 0 title description 12
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30861—Retrieval from the Internet, e.g. browsers
- G06F17/30873—Retrieval from the Internet, e.g. browsers by navigation, e.g. using categorized browsing, portals, synchronized browsing, visual networks of documents, virtual worlds or tours
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30861—Retrieval from the Internet, e.g. browsers
- G06F17/30864—Retrieval from the Internet, e.g. browsers by querying, e.g. search engines or meta-search engines, crawling techniques, push systems
- G06F17/30867—Retrieval from the Internet, e.g. browsers by querying, e.g. search engines or meta-search engines, crawling techniques, push systems with filtering and personalisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Means et al. | Extensible linear floating point SIMD neurocomputer array processor | |
Hirota et al. | Fuzzy logic neural networks: Design and computations | |
Jackson et al. | Distributing back propagation networks over the Intel iPSC/860 hypercube | |
Krikelis | A novel massively associative processing architecture for the implementation of artificial neural networks | |
Alippi et al. | Hardware requirements to digital VLSI implementation of neural networks | |
Nigri et al. | Silicon compilation of neural networks | |
Bahi et al. | A hybrid approach for Arabic speech recognition | |
Hoang et al. | A compiler for multiprocessor DSP implementation | |
Schwarz et al. | A CMOS-array-computer with on-chip communication hardware developed for massively parallel applications | |
Kamangar et al. | Efficient implementation of connectionist models on MIMD parallel processors using chordal ring topologies | |
Fan et al. | A generalized simultaneous access dictionary machine | |
Means et al. | Piriform model execution on a neurocomputer | |
Nakagawa et al. | SDNN-3: a simple processor architecture for O (1) parallel processing in combinatorial optimization with strictly digital neural networks | |
Chang et al. | Backpropagation algorithm in higher order neural network | |
Shams et al. | Parallel methods for implementations of neural networks | |
Martinelli et al. | Hopfield network with O (N) complexity using a constrained backpropagation learning | |
Haq et al. | New algorithms for balancing binary search trees | |
Pazienti | A systolic array for neural network implementation | |
Barash et al. | The systolic array neurocomputer: Fine-grained parallelism at the synaptic level | |
Kirsanov | Digital architecture for neural networks | |
Przytula et al. | NetMap-software tool for mapping neural networks onto parallel computers | |
Suresh | Implementation of an optimal parallel algorithm for arithmetic expression parsing | |
Wei et al. | Efficient hierarchical interconnection for multiprocessor systems | |
Holden et al. | Generalization and learning in Volterra and radial basis function networks: A theoretical analysis | |
Midorikawa | The parallel processing of neural networks on ring-shaped multiprocessor |