Ko et al., 1996 - Google Patents
Design techniques for high-performance, energy-efficient control logicKo et al., 1996
View PDF- Document ID
- 8272754376489384190
- Author
- Ko U
- Hill A
- Balsara P
- Publication year
- Publication venue
- Proceedings of 1996 International Symposium on Low Power Electronics and Design
External Links
Snippet
This paper investigates delay, power and area of critical components in designing energy- efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30 …
- 238000000034 method 0 title description 10
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making or -braking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making or -braking characterised by the components used
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5955912A (en) | Multiplexer circuits | |
| Kawaguchi et al. | A reduced clock-swing flip-flop (RCSFF) for 63% power reduction | |
| EP0863461B1 (en) | Self-timed pipelined datapath system and asynchronous signal control circuit | |
| US5552738A (en) | High performance energy efficient push pull D flip flop circuits | |
| US5767716A (en) | Noise insensitive high performance energy efficient push pull isolation flip-flop circuits | |
| Chung et al. | A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops | |
| US6002284A (en) | Split-slave dual-path D flip flop | |
| KR100239726B1 (en) | Charge recycling differential logic(crdl) circuit and storage elements and device using the same | |
| US6590423B1 (en) | Digital circuits exhibiting reduced power consumption | |
| Nedovic et al. | Dynamic flip-flop with improved power | |
| Ko et al. | Design techniques for high-performance, energy-efficient control logic | |
| Akl et al. | Single-phase SP-domino: A limited-switching dynamic circuit technique for low-power wide fan-in logic gates | |
| Kursun et al. | Node voltage dependent subthreshold leakage current characteristics of dynamic circuits | |
| Wu et al. | Low-power design of sequential circuits using a quasi-synchronous derived clock | |
| Alioto et al. | Performance evaluation of adiabatic gates | |
| Kanojia et al. | Design implementation of a low-power 16T 1-bit hybrid full adder | |
| Ko et al. | High performance, energy efficient master-slave flip-flop circuits | |
| Chang et al. | A novel low power low voltage full adder cell | |
| Ding et al. | A dual-rail static edge-triggered latch | |
| Rjoub et al. | Low-power domino logic multiplier using low-swing technique | |
| Wu et al. | Low-power sequential circuit design using T flip-flops | |
| Zhu et al. | Low-voltage swing clock distribution schemes | |
| AU2021106257A4 (en) | A boundary circuit for interfacing an adiabatic circuit with a cmos circuit | |
| Ko et al. | Hybrid dual-threshold design techniques for high-performance processors with low-power features | |
| Purohit et al. | Design-space exploration of energy-delay-area efficient coarse-grain reconfigurable datapath |