[go: up one dir, main page]

Barzilai et al., 1983 - Google Patents

Simulating pass transistor circuits using logic simulation machines

Barzilai et al., 1983

Document ID
8149406627812738482
Author
Barzilai Z
Huisman L
Silberman G
Tang D
Woo L
Publication year
Publication venue
20th Design Automation Conference Proceedings

External Links

Snippet

An algorithm for pass transistor simulation using the Yorktown Simulation Engine (YSE) is outlined. Implementing this algorithm yields an efficient tool for custom VLSI circuit design verification and fault simulation. Modeling of circuits under this environment is defined …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/70—Fault tolerant, i.e. transient fault suppression

Similar Documents

Publication Publication Date Title
Bryant Symbolic verification of MOS circuits
Abraham et al. An algorithm for the accurate reliability evaluation of triple modular redundancy networks
Bryant MOSSIM: A switch-level simulator for MOS LSI
Bryant A survey of switch-level algorithms
US5884066A (en) Method and apparatus for a trace buffer in an emulation system
Cho et al. Test pattern generation for sequential MOS circuits by symbolic fault simulation
Sridhar et al. A functional approach to testing bit-sliced microprocessors
Cherry Pearl: A CMOS timing analyzer
Barzilai et al. Simulating pass transistor circuits using logic simulation machines
Abadir et al. Functional test generation for digital circuits described using binary decision diagrams
Ghosh Behavioral-level fault simulation
Pandey et al. Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
Newton Timing, logic and mixed-mode simulation for large MOS integrated circuits
Schuster et al. Concurrent fault simulation of MOS digital circuits
Blaauw et al. Automatic generation of behavioral models from switch-level descriptions
KR20020077032A (en) Logic event simulation
Saab et al. Hierarchical multi-level fault simulation of large systems
Srinivas et al. Formal verification of digital circuits using hybrid simulation
Breuer et al. Digital system simulation: Current status and future trends or darwin's theory of simulation
US6553549B1 (en) Static timing analysis with simulations on critical path netlists generated by static timing analysis tools
Zhu et al. SatIn: Hardware for Boolean Satisfiability Inference
Lewis Hardware accelerators for timing simulation of VLSI digital circuits
Bening Developments in Computer Simulation of Gate Level Physical Logic-a Tutorial
Barzilai et al. Using a hardware simulation engine for custom MOS structured designs
Kang et al. Accurate logic simulation by overcoming the unknown value propagation problem