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Mohamed et al., 2002 - Google Patents

A scheme for implementing address translation storage buffers

Mohamed et al., 2002

Document ID
8008993736485315246
Author
Mohamed A
Sagahyroon A
Publication year
Publication venue
IEEE CCECE2002. Canadian Conference on Electrical and Computer Engineering. Conference Proceedings (Cat. No. 02CH37373)

External Links

Snippet

In this paper we present a novel and efficient scheme to implement address translation storage buffers (TSBs). A TSB is tin operating system data structure that caches the most recent address translations. In the proposed approach, a policy of resizing and dynamically …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
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    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
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    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
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    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
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    • G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database

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