[go: up one dir, main page]

Abi Khaled - Google Patents

Congestion Management with feedback queue.

Abi Khaled

View PDF
Document ID
7923236092452748379
Author
Abi Khaled A

External Links

Snippet

The phenomenon of HOL (Head of Line) blocking occurs in communication where the data packets are under some conditions stopped waiting for the appropriate time for routing. This will cause communication delay in the network. Considerable research has been initiated by …
Continue reading at repository.tudelft.nl (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/253—Connections establishment or release between ports
    • H04L49/254—Centralized controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems
    • H04L12/56—Packet switching systems
    • H04L12/5693—Queue scheduling in packet switching networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding through a switch fabric
    • H04L49/256—Routing or path finding in ATM switching fabrics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/50—Overload detection; Overload protection
    • H04L49/505—Corrective Measures, e.g. backpressure
    • H04L49/506—Backpressure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/101—Crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Switching fabric construction
    • H04L49/103—Switching fabric construction using shared central buffer, shared memory, e.g. time switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic regulation in packet switching networks
    • H04L47/10—Flow control or congestion control
    • H04L47/24—Flow control or congestion control depending on the type of traffic, e.g. priority or quality of service [QoS]
    • H04L47/2441—Flow classification
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services or operations
    • H04L49/201—Multicast or broadcast
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G06F15/163—Interprocessor communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic regulation in packet switching networks
    • H04L47/50—Queue scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks

Similar Documents

Publication Publication Date Title
Duato et al. A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks
Ngai et al. A framework for adaptive routing in multicomputer networks
Singh Load-balanced routing in interconnection networks
Duato Deadlock-free adaptive routing algorithms for multicomputers: Evaluation of a new algorithm
US20070121499A1 (en) Method of and system for physically distributed, logically shared, and data slice-synchronized shared memory switching
García et al. Dynamic evolution of congestion trees: Analysis and impact on switch architecture
Smai et al. Global reactive congestion control in multicomputer networks
Oveis-Gharan et al. Efficient dynamic virtual channel organization and architecture for NoC systems
Zahavi et al. Distributed adaptive routing for big-data applications running on data center networks
Dai et al. A cost-efficient router architecture for HPC inter-connection networks: design and implementation
Lysne et al. Simple deadlock-free dynamic network reconfiguration
Das et al. VCS: a method of in-order packet delivery for adaptive NoC routing
Papaphilippou et al. Hipernetch: High-performance FPGA network switch
Escudero-Sahuquillo et al. OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees
Daneshtalab et al. CARS: Congestion-aware request scheduler for network interfaces in NoC-based manycore systems
Yébenes et al. Straightforward solutions to reduce HoL blocking in different Dragonfly fully-connected interconnection patterns
Escudero-Sahuquillo et al. FBICM: Efficient congestion management for high-performance networks using distributed deterministic routing
Abi Khaled Congestion Management with feedback queue.
Villar et al. An integrated solution for QoS provision and congestion management in high-performance interconnection networks using deterministic source-based routing
Garcia et al. Recn-dd: A memory-efficient congestion management technique for advanced switching
Lugones et al. Modeling adaptive routing protocols in high speed interconnection networks
Zhang et al. An area-efficient DAMQ buffer with congestion control support
Escudero‐Sahuquillo et al. Cost‐effective queue schemes for reducing head‐of‐line blocking in fat‐trees
Gómez et al. A HoL-blocking aware mechanism for selecting the upward path in fat-tree topologies
Kim Planar-adaptive routing(PAR): low-cost adaptive networks for multiprocessors