[go: up one dir, main page]

Xin et al., 2023 - Google Patents

A parallel and updatable architecture for FPGA-based packet classification with large-scale rule sets

Xin et al., 2023

Document ID
7668233644639990487
Author
Xin Y
Li W
Xie G
Xu Y
Wang Y
Publication year
Publication venue
IEEE Micro

External Links

Snippet

As a programmable hardware, field-programmable gate array (FPGA) provides more opportunities for algorithmic network packet classification. Despite more than 10 years of research, the most actively investigated pipeline architectures still struggle to support fast …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G06F17/30386Retrieval requests
    • G06F17/30424Query processing
    • G06F17/30442Query optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30943Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type
    • G06F17/30946Information retrieval; Database structures therefor; File system structures therefor details of database functions independent of the retrieved data type indexing structures
    • G06F17/30961Trees
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/3061Information retrieval; Database structures therefor; File system structures therefor of unstructured textual data
    • G06F17/30634Querying
    • G06F17/30657Query processing
    • G06F17/30675Query execution
    • G06F17/30678Query execution using boolean model
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation

Similar Documents

Publication Publication Date Title
US8780926B2 (en) Updating prefix-compressed tries for IP route lookup
Ganegedara et al. A scalable and modular architecture for high-performance packet classification
Waldvogel et al. Scalable high-speed prefix matching
Le et al. Scalable tree-based architectures for IPv4/v6 lookup using prefix partitioning
Vamanan et al. TreeCAM: decoupling updates and lookups in packet classification
Xin et al. A parallel and updatable architecture for FPGA-based packet classification with large-scale rule sets
Hsieh et al. Many-field packet classification for software-defined networking switches
Xin et al. FPGA-based updatable packet classification using TSS-combined bit-selecting tree
Le et al. Memory-efficient and scalable virtual routers using FPGA
Perez et al. A configurable packet classification architecture for software-defined networking
Le et al. Scalable high throughput and power efficient ip-lookup on fpga
Le et al. Scalable high-throughput sram-based architecture for ip-lookup using FPGA
Shi et al. MsBV: A memory compression scheme for bit-vector-based classification lookup tables
Veeramani et al. Efficient IP lookup using hybrid trie-based partitioning of TCAM-based open flow switches
Erdem et al. Hierarchical hybrid search structure for high performance packet classification
Xin et al. Updatable packet classification on FPGA with bounded worst-case performance
Xin et al. Recursive multi-tree construction with efficient rule sifting for packet classification on FPGA
Chang et al. Dynamic multiway segment tree for IP lookups and the fast pipelined search engine
Erdem Pipelined hierarchical architecture for high performance packet classification
Jiang et al. Multi-terabit IP lookup using parallel bidirectional pipelines
Saxena et al. Scalable, high-speed on-chip-based NDN name forwarding using FPGA
Pao et al. Parallel tree search: An algorithmic approach for multi-field packet classification
Park et al. An efficient IP address lookup algorithm based on a small balanced tree using entry reduction
Yu A memory-and time-efficient on-chip TCAM minimizer for IP lookup
Hsiao et al. A high-throughput and high-capacity IPv6 routing lookup system