Beattie et al., 2002 - Google Patents
Error bounds for capacitance extraction via window techniquesBeattie et al., 2002
- Document ID
- 7620649029377103695
- Author
- Beattie M
- Pileggi L
- Publication year
- Publication venue
- IEEE transactions on computer-aided design of integrated circuits and systems
External Links
Snippet
The overwhelming size of the capacitance extraction problem forces designers to localize the capacitive coupling and determine a distance (a" window") outside of which the mutual capacitance between two wires is" small enough" to ignore. The primary difficulties with such …
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- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
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- G06F17/5018—Computer-aided design using simulation using finite difference methods or finite element methods
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- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
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- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
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- G06F17/30861—Retrieval from the Internet, e.g. browsers
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