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Soma et al., 2014 - Google Patents

An On-Chip Delay Measurement Technique for Small-Delay Defect Detection Using Signature Registers

Soma et al., 2014

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Document ID
7259280562835405632
Author
Soma R
Tabassum Z
Prathap S
Publication year
Publication venue
IJCSNS

External Links

Snippet

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
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    • G01R31/318555—Control logic
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    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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    • G01R31/318558—Addressing or selecting of subparts of the device under test
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    • G01R31/2851—Testing of integrated circuits [IC]
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    • G—PHYSICS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

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