Padmanabha et al., 2013 - Google Patents
Trace based phase prediction for tightly-coupled heterogeneous coresPadmanabha et al., 2013
View PDF- Document ID
- 7218610402189111437
- Author
- Padmanabha S
- Lukefahr A
- Das R
- Mahlke S
- Publication year
- Publication venue
- Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
External Links
Snippet
Heterogeneous multicore systems are composed of multiple cores with varying energy and performance characteristics. A controller dynamically detects phase changes in applications and migrates execution onto the most efficient core that meets the performance …
- 235000019580 granularity 0 abstract description 41
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
- G06F9/3842—Speculative instruction execution
- G06F9/3844—Speculative instruction execution using dynamic prediction, e.g. branch history table
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
- G06F1/3234—Action, measure or step performed to reduce power consumption
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3466—Performance evaluation by tracing or monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5094—Allocation of resources, e.g. of the central processing unit [CPU] where the allocation takes into account power or heat criteria
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformations of program code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Padmanabha et al. | Trace based phase prediction for tightly-coupled heterogeneous cores | |
| Lukefahr et al. | Composite cores: Pushing heterogeneity into a core | |
| Gupta et al. | Dypo: Dynamic pareto-optimal configuration selection for heterogeneous mpsocs | |
| Rotenberg et al. | A trace cache microarchitecture and evaluation | |
| US9639363B2 (en) | Heterogeneity within a processor core | |
| Patsilaras et al. | Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era | |
| Padmanabha et al. | DynaMOS: Dynamic schedule migration for heterogeneous cores | |
| Kondguli et al. | A case for a more effective, power-efficient turbo boosting | |
| Atta et al. | Self-contained, accurate precomputation prefetching | |
| Srinivasan et al. | Exploring heterogeneity within a core for improved power efficiency | |
| Lukefahr et al. | Exploring fine-grained heterogeneity with composite cores | |
| Jarus et al. | Top-down characterization approximation based on performance counters architecture for amd processors | |
| Padmanabha et al. | Mirage cores: The illusion of many out-of-order cores using in-order hardware | |
| Sawalha et al. | Energy-efficient phase-aware scheduling for heterogeneous multicore processors | |
| Premillieu et al. | Syrant: Symmetric resource allocation on not-taken and taken paths | |
| Tullsen et al. | Computing along the critical path | |
| Wu et al. | A HW/SW co-designed heterogeneous multi-core virtual machine for energy-efficient general purpose computing | |
| Zhang et al. | Adaptive front-end throttling for superscalar processors | |
| Boran et al. | Performance modelling and dynamic scheduling on heterogeneous-ISA multi-core architectures | |
| Vandeputte et al. | Exploiting program phase behavior for energy reduction on multi-configuration processors | |
| Mehta et al. | Fetch halting on critical load misses | |
| Lee et al. | Simultaneous and speculative thread migration for improving energy efficiency of heterogeneous core architectures | |
| Mitra et al. | Performance modeling of shared memory multiple issue multicore machines | |
| Nagpal et al. | Criticality guided energy aware speculation for speculative multithreaded processors | |
| Manakul et al. | Modeling dwarfs for workload characterization |