[go: up one dir, main page]

Chall, 1991 - Google Patents

4955131 Method of building a variety of complex high performance IC devices

Chall, 1991

Document ID
6559194324018814093
Author
Chall L
Publication year
Publication venue
Microelectronics Reliability

External Links

Continue reading at scholar.google.com (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes

Similar Documents

Publication Publication Date Title
EP0481703B1 (en) Interconnect substrate having integrated circuit for programmable interconnection and sample testing
US4241307A (en) Module interconnection testing scheme
US4476431A (en) Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes
US6822469B1 (en) Method for testing multiple semiconductor wafers
US5525912A (en) Probing equipment and a probing method
EP0315792A3 (en) Interconnection system for integrated circuit chips
JP6185969B2 (en) Method and apparatus for testing a device using serially controlled resources
US7003697B2 (en) Apparatus having pattern scrambler for testing a semiconductor device and method for operating same
EP0438705B1 (en) Integrated circuit driver inhibit control method for test
WO1992011643A1 (en) Integrated parity-based testing for integrated circuits
CN101017182A (en) Wafer-level burn-in and test
CN111183517B (en) IC die with parallel PRBS testing of interposer
Chall 4955131 Method of building a variety of complex high performance IC devices
Funakoshi 4954772 Test method of an electrostatic breakdown of a semiconductor device and an apparatus therefor
EP1099953B1 (en) Semiconductor device with testing capability
EP1081757B1 (en) Multichip module packaging process for known good die burn-in
US6222211B1 (en) Memory package method and apparatus
US6521986B2 (en) Slot apparatus for programmable multi-chip module
Fuchs et al. Wafer-scale integration: Architectures and algorithms
US6557244B1 (en) Wafer level board/card assembly apparatus
Eichelberger et al. 4937203 Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
Rhodes et al. 4937475 Laser programmable integrated circuit
Banker Designing ASICs for use with multichip modules
US6225821B1 (en) Package migration for related programmable logic devices
Chall 4937659 Interconnection system for integrated circuit chips