Peng et al., 2016 - Google Patents
FPGA-based parallel hardware architecture for SIFT algorithmPeng et al., 2016
- Document ID
- 6417924942798653960
- Author
- Peng J
- Liu Y
- Lyu C
- Li Y
- Zhou W
- Fan K
- Publication year
- Publication venue
- 2016 IEEE International Conference on Real-time Computing and Robotics (RCAR)
External Links
Snippet
A parallel hardware architecture for real-time image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm has been presented. The proposed parallel hardware architecture is completely stand-alone; it reads the input data directly from …
- 238000004422 calculation algorithm 0 title abstract description 40
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06K—RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K9/00—Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
- G06K9/36—Image preprocessing, i.e. processing the image information without deciding about the identity of the image
- G06K9/46—Extraction of features or characteristics of the image
- G06K9/4604—Detecting partial patterns, e.g. edges or contours, or configurations, e.g. loops, corners, strokes, intersections
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06K—RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K9/00—Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
- G06K9/36—Image preprocessing, i.e. processing the image information without deciding about the identity of the image
- G06K9/46—Extraction of features or characteristics of the image
- G06K9/50—Extraction of features or characteristics of the image by analysing segments intersecting the pattern segments obtained by the intersection of the pattern with a scanning pattern, e.g. random scanning, circular scanning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06K—RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K9/00—Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
- G06K9/62—Methods or arrangements for recognition using electronic means
- G06K9/6201—Matching; Proximity measures
- G06K9/6202—Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching
- G06K9/6203—Shifting or otherwise transforming the patterns to accommodate for positional errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30244—Information retrieval; Database structures therefor; File system structures therefor in image databases
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20112—Image segmentation details
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T17/00—Three dimensional [3D] modelling, e.g. data description of 3D objects
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Peng et al. | FPGA-based parallel hardware architecture for SIFT algorithm | |
Lin et al. | CODE: Coherence based decision boundaries for feature correspondence | |
Jiang et al. | SIFT hardware implementation for real-time image feature extraction | |
CN104221031B (en) | The method that image feature and fixed reference feature are matched and its integrated circuit used | |
Ghaffari et al. | Analysis and comparison of FPGA-based histogram of oriented gradients implementations | |
Chang et al. | FPGA-based detection of SIFT interest keypoints | |
Vourvoulakis et al. | Fully pipelined FPGA-based architecture for real-time SIFT extraction | |
Hsiao et al. | Multilayered image processing for multiscale Harris corner detection in digital realization | |
Tu et al. | Design and implementation of robust visual servoing control of an inverted pendulum with an FPGA-based image co-processor | |
CN111583093A (en) | Hardware implementation method for ORB feature point extraction with good real-time performance | |
CN109522906A (en) | The quick SIFT feature extracting method of low complex degree based on FPGA | |
Kang et al. | Image registration based on harris corner and mutual information | |
Suzuki et al. | SIFT-based low complexity keypoint extraction and its real-time hardware implementation for full-HD video | |
Zhang et al. | Hierarchical and parallel pipelined heterogeneous SoC for embedded vision processing | |
He et al. | A real-time and high precision hardware implementation of RANSAC algorithm for visual SLAM achieving mismatched feature point pair elimination | |
Lyu et al. | Design of a high speed 360-degree panoramic video acquisition system based on fpga and usb 3.0 | |
Zhu et al. | A 135-frames/s 1080p 87.5-mw binary-descriptor-based image feature extraction accelerator | |
Suzuki et al. | Low complexity keypoint extraction based on SIFT descriptor and its hardware implementation for full-HD 60 fps video | |
Zhang et al. | FPGA-based implementation of hand gesture recognition using convolutional neural network | |
Fan et al. | ASP-SIFT: Using analog signal processing architecture to accelerate keypoint detection of SIFT algorithm | |
Chen et al. | Research on design and verification of sobel image edge detection based on high level synthesis | |
Aguilar-González et al. | Robust feature extraction algorithm suitable for real-time embedded applications | |
Brenot et al. | FPGA based hardware acceleration of a BRIEF correlator module for a monocular SLAM application | |
Wang et al. | Design of real-time SIFT feature extraction | |
Xiao et al. | Real-time scene recognition on embedded system with SIFT keypoints and a new descriptor |