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Shetty, 2020 - Google Patents

Enabling the Generation of Behavioral System-on Chip (SoC)

Shetty, 2020

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Document ID
6039638592256489656
Author
Shetty S
Publication year

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The thesis aims to enable the generation of complete behavioral heterogenous System-on- Chip (SoC) through two main ideas: First, an automatic bus generator that takes as input the bus characteristics and memory map of all the components in the SoC generating a …
Continue reading at utd-ir.tdl.org (PDF) (other versions)

Classifications

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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
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    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
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    • G06F17/5045Circuit design
    • G06F17/5054Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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    • G06COMPUTING; CALCULATING; COUNTING
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    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Programme initiating; Programme switching, e.g. by interrupt
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    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
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    • G06F8/00Arrangements for software engineering
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    • G06F8/44Encoding
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    • G06F13/14Handling requests for interconnection or transfer
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
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    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements

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