Weiss et al., 1999 - Google Patents
A new scalable DSP architecture for system on chip (SoC) domainsWeiss et al., 1999
View PDF- Document ID
- 5768887906948934042
- Author
- Weiss M
- Engel F
- Fettweis G
- Publication year
- Publication venue
- 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No. 99CH36258)
External Links
Snippet
The ongoing advances in semiconductor technology are the enabler for complete system on chip (SoC) solutions. In this SoC domain digital signal processors (DSPs) are employed to carry out software driven digital signal processing tasks. Although DSPs could still be …
- 235000019800 disodium phosphate 0 title abstract description 51
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/147—Discrete orthonormal transforms, e.g. discrete cosine transform, discrete sine transform, and variations therefrom, e.g. modified discrete cosine transform, integer transforms approximating the discrete cosine transform
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/16—Constructional details or arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9647731B2 (en) | Reconfigurable network on a chip (NoC) radio through reduced instruction set computer (RISC) agents by overwriting program store for different phases of demodulation | |
| US7200138B2 (en) | Physical medium dependent sub-system with shared resources for multiport xDSL system | |
| US6631461B2 (en) | Dyadic DSP instructions for digital signal processors | |
| EP2013762B1 (en) | General purpose array processing | |
| WO2002037259A1 (en) | Methods and apparatus for efficient complex long multiplication and covariance matrix implementation | |
| CN101101540A (en) | Method and apparatus for flexible data types | |
| CN101238455A (en) | Programmable digital signal processor including a clustered SIMD microarchitecture configured to execute complex vector instructions | |
| Weiss et al. | A new scalable DSP architecture for system on chip (SoC) domains | |
| Beerel et al. | Low power and energy efficient asynchronous design | |
| Richter et al. | A platform-based highly parallel digital signal processor | |
| US7669042B2 (en) | Pipeline controller for context-based operation reconfigurable instruction set processor | |
| TAI et al. | Design and efficient implementation of a modulated complex lapped transform processor using pipelining technique | |
| Jonsson et al. | Real-time scheduling for pipelined execution of data flow graphs on a realistic multiprocessor architecture | |
| Schmidt-Knorreck et al. | Flexible front-end processing for software defined radio applications using application specific instruction-set processors | |
| Eberli et al. | An IEEE 802.11 a baseband receiver implementation on an application specific processor | |
| EP1546868B1 (en) | Superpipelined vliw processor addressing bypass-loop speed limitation | |
| Weiss et al. | TOOLS AND SYSTEMSUPPORT FOR A NEW SCALABLE DSP ARCHITECTURE | |
| US20040022192A1 (en) | Bit stream processor | |
| Heysters et al. | Flexibility of the Montium Word-Level Reconfigurable Processing Tile | |
| Quan et al. | FPGA resource efficient M-PSK detector for large MIMO and multiuser systems | |
| Bolzer et al. | A new vector processor architecture for high performance signal processing | |
| Lee et al. | Low power reconfigurable macro-operation signal processing for wireless communications | |
| Meier et al. | Efficient and reusable time-sharing architectures for equalizer structures | |
| Woh | Architecture and analysis for next generation mobile signal processing | |
| Dahnoun et al. | The implementation of a modem based on quadrature amplitude modulation using the TMS320C6201 DSP |