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Kulkarni et al., 2024 - Google Patents

Physical Design: Methodologies and Developments

Kulkarni et al., 2024

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Document ID
574078553711383749
Author
Kulkarni A
Chopde A
Publication year
Publication venue
arXiv preprint arXiv:2409.04726

External Links

Snippet

The design and production of VLSI chips is a multilevel heirarchical process. As the demand for reduced die-area and technology nodes becomes prevalent, it gets increasingly challenging to optimize Power, Performance and Area (PPA) parameters to accommodate …
Continue reading at arxiv.org (PDF) (other versions)

Classifications

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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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