[go: up one dir, main page]

Li et al., 2018 - Google Patents

Variability-aware double-patterning layout optimization for analog circuits

Li et al., 2018

View PDF
Document ID
55565136708100067
Author
Li Y
Perez V
Tripathi V
Lee Z
Tseng I
Ong J
Publication year
Publication venue
Design-Process-Technology Co-optimization for Manufacturability XII

External Links

Snippet

The semiconductor industry has adopted multi-patterning techniques to manage the delay in the extreme ultraviolet lithography technology. During the design process of double- patterning lithography layout masks, two polygons are assigned to different masks if their …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081Layout analysis, e.g. layout verification, design rule check
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5068Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5072Floorplanning, e.g. partitioning, placement
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5045Circuit design
    • G06F17/505Logic synthesis, e.g. technology mapping, optimisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/20Handling natural language data
    • G06F17/21Text processing
    • G06F17/22Manipulating or registering by use of codes, e.g. in sequence of text characters
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861Retrieval from the Internet, e.g. browsers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/20Handling natural language data
    • G06F17/27Automatic analysis, e.g. parsing
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/12Design for manufacturability
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/14Originals characterised by structural details, e.g. supports, cover layers, pellicle rings
    • G03F1/144Auxiliary patterns; Corrected patterns, e.g. proximity correction, grey level masks
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes

Similar Documents

Publication Publication Date Title
US11763060B2 (en) Automatic generation of layouts for analog integrated circuits
US10943052B2 (en) Integrated circuit design method, system and computer program product
US10846456B2 (en) Integrated circuit modeling methods and systems
Du et al. DSA-aware detailed routing for via layer optimization
US12093625B2 (en) Integrated circuit design method, system and computer program product
US12118287B2 (en) Automatic generation of sub-cells for an analog integrated circuit
US9965579B2 (en) Method for designing and manufacturing an integrated circuit, system for carrying out the method, and system for verifying an integrated circuit
Lai et al. Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?
Wang et al. Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond
US20230237234A1 (en) Integrated circuit design method, system and computer program product
Li et al. Variability-aware double-patterning layout optimization for analog circuits
Neogi et al. Design space analysis of novel interconnect constructs for 22nm FDX technology
Ban et al. Layout induced variability and manufacturability checks in FinFETs process
Katakamsetty et al. Cutting-edge CMP modeling for front-end-of-line (FEOL) and full stack hotspot detection for advanced technologies
Kahng et al. Auxiliary pattern-based optical proximity correction for better printability, timing, and leakage control
CN114912399A (en) Method and system for process technology evaluation and method for process technology evaluation
Duan et al. Design technology co-optimization for 14/10nm metal1 double patterning layer
Yokoyama et al. Localization concept of re-decomposition area to fix hotspots for LELE process
Mattii et al. Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules
Zhao et al. Enhancing manufacturability of standard cells by using DTCO methodology
Lee et al. A random approach of test macro generation for early detection of hotspots
Hamouda et al. Efficient model-based dummy-fill OPC correction flow for deep sub-micron technology nodes
Su et al. Projection-based high coverage fast layout decomposing algorithm of metal layer for accelerating lithography friendly design at full chip level
Mohyeldin et al. Quantifying electrical impacts on redundant wire insertion in 7nm unidirectional designs
US11972191B2 (en) System and method for providing enhanced net pruning