Ferrer et al., 2009 - Google Patents
Quality of Service in NoC for Reconfigurable Space ApplicationsFerrer et al., 2009
- Document ID
- 5465509039916564263
- Author
- Ferrer A
- Parkes S
- Mendham P
- Publication year
- Publication venue
- 2009 NASA/ESA Conference on Adaptive Hardware and Systems
External Links
Snippet
Configurable system-on-chip (SoC) solutions based on state-of-the art FPGA are a good candidate to fulfill the requirements of future high end onboard payload applications. Reliability, performance and flexibility provided by SoCs can be further extended using a …
- 238000004891 communication 0 abstract description 11
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding through a switch fabric
- H04L49/253—Connections establishment or release between ports
- H04L49/254—Centralized controller, i.e. arbitration or scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. local area networks [LAN], wide area networks [WAN]
- H04L12/46—Interconnection of networks
- H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
- H04L12/462—LAN interconnection over a bridge based backbone
- H04L12/4625—Single bridge functionality, e.g. connection of two networks over a single bridge
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic regulation in packet switching networks
- H04L47/10—Flow control or congestion control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Switching fabric construction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Queuing arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/64—Hybrid switching systems
- H04L12/6402—Hybrid switching fabrics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services or operations
- H04L49/201—Multicast or broadcast
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/60—Hybrid or multiprotocol packet, ATM or frame switches
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP3776231B1 (en) | Procedures for implementing source based routing within an interconnect fabric on a system on chip | |
US6947433B2 (en) | System and method for implementing source based and egress based virtual networks in an interconnection network | |
US7039058B2 (en) | Switched interconnection network with increased bandwidth and port count | |
EP1552669B1 (en) | Integrated circuit and method for establishing transactions | |
Rijpkema et al. | A router architecture for networks on silicon | |
Rijpkema et al. | Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip | |
US7046633B2 (en) | Router implemented with a gamma graph interconnection network | |
US8014401B2 (en) | Electronic device and method of communication resource allocation | |
US20080205432A1 (en) | Network-On-Chip Environment and Method For Reduction of Latency | |
WO2002065700A2 (en) | An interconnection system | |
Nguyen et al. | A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs | |
Ferrer et al. | Quality of Service in NoC for Reconfigurable Space Applications | |
Berejuck et al. | Evaluation of silicon consumption for a connectionless network-on-chip | |
Salah et al. | Design of a 2d mesh-torus router for network on chip | |
Lin et al. | Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network | |
Florit et al. | SpaceFibre Multi-Lane Routing Switch IP | |
Rijpkema et al. | Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip (Extended Version) | |
Regidor et al. | Implementation of a parametrizable router architecture for networks-on-chip (NoC) with quality of service (QoS) support | |
Mavroidis | The IRAM Network Interface | |
Kim et al. | An Asynchronous NoC Router Architecture Supporting Quality-of-Service | |
IOANNIS | Design an Efficient Router for Network on Chip Design |