Sahu et al., 2020 - Google Patents
On-Chip Learning in Spintronics-Based Spiking Neural Network for Handwritten Digit RecognitionSahu et al., 2020
- Document ID
- 5198862292232108717
- Author
- Sahu U
- Goyal K
- Bhowmik D
- Publication year
- Publication venue
- 2020 5th IEEE International Conference on Emerging Electronics (ICEE)
External Links
Snippet
Spiking Neural Network (SNN) has been shown to consume very low power for inference tasks, but training of such SNN has remained a challenge. In this paper, we use biologically plausible Spike-Time-Dependent-Plasticity-enabled learning to train the SNN through …
- 230000001537 neural 0 title abstract description 14
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/0635—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means using analogue means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/08—Learning methods
- G06N3/082—Learning methods modifying the architecture, e.g. adding or deleting nodes or connections, pruning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computer systems based on biological models
- G06N3/02—Computer systems based on biological models using neural network models
- G06N3/04—Architectures, e.g. interconnection topology
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06N—COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N99/00—Subject matter not provided for in other groups of this subclass
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhang et al. | Hybrid memristor-CMOS neurons for in-situ learning in fully hardware memristive spiking neural networks | |
| US12141686B2 (en) | Spin orbit torque based electronic neuron | |
| Sengupta et al. | Hybrid spintronic-CMOS spiking neural network with on-chip learning: Devices, circuits, and systems | |
| Jaiswal et al. | Proposal for a leaky-integrate-fire spiking neuron based on magnetoelectric switching of ferromagnets | |
| Ebong et al. | CMOS and memristor-based neural network design for position detection | |
| Sengupta et al. | Probabilistic deep spiking neural systems enabled by magnetic tunnel junction | |
| JP6477924B2 (en) | Memristor neuromorphological circuit and method for training memristor neuromorphological circuit | |
| Cai et al. | Unconventional computing based on magnetic tunnel junction | |
| US11514301B2 (en) | Magnetic domain wall drift for an artificial leaky integrate-and-fire neuron | |
| Srinivasan et al. | Magnetic tunnel junction enabled all-spin stochastic spiking neural network | |
| CN107341539A (en) | neural network processing system | |
| CN107368888B (en) | Brain-like computing systems and their synapses | |
| US10381074B1 (en) | Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors | |
| US11977970B2 (en) | Spintronic computing architecture and method | |
| Lin et al. | Analysis and simulation of capacitor-less ReRAM-based stochastic neurons for the in-memory spiking neural network | |
| Agrawal et al. | Mimicking leaky-integrate-fire spiking neuron using automotion of domain walls for energy-efficient brain-inspired computing | |
| Thomas et al. | Analysis of parasitic effects in a crossbar in CMOS based neuromorphic system for pattern recognition using memristive synapses | |
| Oh et al. | Spiking neural networks with time-to-first-spike coding using TFT-type synaptic device model | |
| Kang et al. | Synaptic weight evolution and charge trapping mechanisms in a synaptic pass-transistor operation with a direct potential output | |
| Sengupta et al. | Stochastic inference and learning enabled by magnetic tunnel junctions | |
| CN108154225A (en) | A kind of neural network chip calculated using simulation | |
| Gupta et al. | On-chip unsupervised learning using STDP in a spiking neural network | |
| Zhou et al. | Neuromorphic Hebbian learning with magnetic tunnel junction synapses | |
| Vatajelu et al. | Fully-connected single-layer stt-mtj-based spiking neural network under process variability | |
| Sheikhfaal et al. | Short-term long-term compute-in-memory architecture: A hybrid spin/CMOS approach supporting intrinsic consolidation |