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Wei et al., 2012 - Google Patents

GLARE: Global and local wiring aware routability evaluation

Wei et al., 2012

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Document ID
4678168948512435939
Author
Wei Y
Sze C
Viswanathan N
Li Z
Alpert C
Reddy L
Huber A
Tellez G
Keller D
Sapatnekar S
Publication year
Publication venue
Proceedings of the 49th Annual Design Automation Conference

External Links

Snippet

Industry routers are very complex and time consuming, and are becoming more so with the explosion in design rules and design for manufacturability requirements that multiply with each technology node. Global routing is just the first phase of a router and serves the dual …
Continue reading at www.ece.umn.edu (PDF) (other versions)

Classifications

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    • G06F17/5022—Logic simulation, e.g. for logic circuit operation
    • G06F17/5031—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
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    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5077—Routing
    • G—PHYSICS
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    • G06F17/5072—Floorplanning, e.g. partitioning, placement
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