[go: up one dir, main page]

Leijten et al., 2003 - Google Patents

Avispa: A massively parallel reconfigurable accelerator

Leijten et al., 2003

Document ID
440333752989149454
Author
Leijten J
Burns G
Huisken J
Waterlander E
van Wel A
Publication year
Publication venue
Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No. 03EX748)

External Links

Snippet

Standards and market uncertainties, non-recurring engineering costs, and lack of access to (or knowledge of) application IP requires the next generation of embedded computing platforms to be fully programmable. In terms of silicon cost and power, practical yet fully …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformations of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes

Similar Documents

Publication Publication Date Title
Lodi et al. A VLIW processor with reconfigurable instruction set for embedded applications
Clark et al. An architecture framework for transparent instruction set customization in embedded processors
US7902866B1 (en) Wires on demand: run-time communication synthesis for reconfigurable computing
DeHon et al. Reconfigurable computing: what, why, and implications for design automation
US7657861B2 (en) Method and device for processing data
Jones et al. An FPGA-based VLIW processor with custom hardware execution
Cardoso et al. XPP-VC: AC compiler with temporal partitioning for the PACT-XPP architecture
US20140137123A1 (en) Microcomputer for low power efficient baseband processing
JP2008539485A (en) Reconfigurable instruction cell array
Cichon et al. Synchronous transfer architecture (STA)
Paul et al. reMORPH: a runtime reconfigurable architecture
Baas et al. AsAP: A fine-grained many-core platform for DSP applications
Cardoso et al. Compilation and Temporal Partitioning for a Coarse-Grain Reconfigurable Architecture
Leijten et al. Avispa: A massively parallel reconfigurable accelerator
Sedcole et al. A reconfigurable platform for real-time embedded video image processing
Weinhardt et al. Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays
Rossi et al. Application space exploration of a heterogeneous run-time configurable digital signal processor
Bauer et al. Efficient resource utilization for an extensible processor through dynamic instruction set adaptation
Becker et al. Scalable processor instruction set extension
Nguyen et al. A survey on reconfigurable system-on-chips
Schoeberl Leros: A tiny microcontroller for FPGAs
Shafique et al. REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set
Schuster et al. Design of a low power pre-synchronization ASIP for multimode SDR terminals
Wallner A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization
Lanuzza et al. MORA: A new coarse-grain reconfigurable array for high throughput multimedia processing