Schauer, 1979 - Google Patents
External Clock Synchronization Plans for the GTD 3 EAX Digital Toll/TandemSchauer, 1979
- Document ID
- 4296846974993056391
- Author
- Schauer R
- Publication year
- Publication venue
- IEEE Transactions on Communications
External Links
Snippet
The GTD 3 EAX local clock was designed with external synchronization in mind. The initial control algorithms and control circuits required a minimum of change to incorporate the ability to maintain clock synchronization with an external timing reference. The …
- 238000000034 method 0 abstract description 3
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/14—Monitoring arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/12—Arrangements providing for calling or supervisory signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/00
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0057—Operations, administration and maintenance [OAM]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/0016—Arrangements providing connection between exchanges
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CA2223708C (en) | Distribution of synchronization in a synchronous optical environment | |
US5673004A (en) | Method and circuit for controlling digital processing phase-locked loop for network synchronization | |
US5638379A (en) | Encoding system for distribution of synchronization | |
US5742208A (en) | Signal generator for generating a jitter/wander output | |
US5886996A (en) | Synchronous digital communication system with a hierarchical synchronization network | |
EP1665695A1 (en) | System for synchronous sampling and time-of-day clocking using an encoded time signal | |
US6707828B1 (en) | Synchronization of a network element in a synchronous digital communications network | |
Abate et al. | AT&T's new approach to the synchronization of telecommunication networks | |
Schauer | External Clock Synchronization Plans for the GTD 3 EAX Digital Toll/Tandem | |
Saltzberg et al. | Digital data system: Network synchronization | |
Yamato et al. | Synchronization of a PCM integrated telephone network | |
US4498059A (en) | Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit | |
Kihara | Performance aspects of reference clock distribution for evolving digital networks | |
Munter | Synchronized clock for DMS-100 family | |
CA1215436A (en) | Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit | |
WO1994021048A1 (en) | Method of generating a clock signal by means of a phase-locked loop and a phase-locked loop | |
US4510462A (en) | Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit | |
Biholar | CONTRIBUTION TO T1 STANDARDS PROJECT | |
Metz et al. | No. 4 ESS: Network clock synchronization | |
Datta et al. | Synchronization of multi-exchange local network by bit-by-bit method | |
Bass et al. | A redundant timing source for digital telecommunication network synchronization | |
CA2254225C (en) | Phase modulated reduction of clock wander in synchronous wide area networks | |
Li et al. | Fast computation of time deviation and modified Allan deviation for telecommunications clock stability characterization | |
CA1263899A (en) | Synchronization circuitry for duplex digital span equipment | |
Imaoka et al. | Time signal distribution in communication networks based on synchronous digital hierarchy |