[go: up one dir, main page]

Sengupta, 2020 - Google Patents

Test Cost Reduction of 3D Stacked ICs: Test Planning and Test Flow Selection

Sengupta, 2020

View PDF
Document ID
4282477652007487871
Author
Sengupta B
Publication year

External Links

Snippet

Ever higher levels of integration within the Integrated Circuit (IC) to meet progressively widening scope of its application in respect of functionality, size, performance and manufacturing issues inspired development of the three-dimensional (3D) Stacked IC as a …
Continue reading at portal.research.lu.se (PDF) (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06551Conductive connections on the side of the device
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design

Similar Documents

Publication Publication Date Title
Marinissen et al. A structured and scalable test access architecture for TSV-based 3D stacked ICs
Noia et al. Test-architecture optimization and test scheduling for TSV-based 3-D stacked ICs
Marinissen et al. Testing 3D chips containing through-silicon vias
JP6002124B2 (en) Test architecture for TSV-based 3D stacked IC
Marinissen et al. A DfT architecture for 3D-SICs based on a standardizable die wrapper
Chi et al. Post-bond testing of 2.5 D-SICs and 3D-SICs containing a passive silicon interposer base
Noia et al. Optimization methods for post-bond die-internal/external testing in 3D stacked ICs
SenGupta et al. Scheduling tests for 3D stacked chips under power constraints
Appello et al. System-in-package testing: problems and solutions
Wang et al. Built-in self-test and test scheduling for interposer-based 2.5 D IC
JPH04112555A (en) Semiconductor integrated circuit device
Sengupta Test Cost Reduction of 3D Stacked ICs: Test Planning and Test Flow Selection
Franzon et al. Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management
Sengupta Test Cost Reduction of 3D Stacked ICs
SenGupta et al. Test planning for core-based integrated circuits under power constraints
Wang et al. Testing of interposer-based 2.5 D integrated circuits
Agrawal et al. A distributed, reconfigurable, and reusable BIST infrastructure for test and diagnosis of 3-D-Stacked ICs
Tadayon et al. Moore’s law and the future of test
Gupta et al. Test planning for core-based 3D stacked ICs with through-silicon vias
Panth et al. Probe-pad placement for prebond test of 3-D ICs
SenGupta et al. Test planning and test access mechanism design for stacked chips using ILP
Chi et al. Low-cost post-bond testing of 3-D ICs containing a passive silicon interposer base
Gulve et al. Test methodology automation for multi-die package realization
Pradhan et al. Optimal stacking of SOCs in a 3D-SIC for post-bond testing
Koneru et al. Test and design-for-testability solutions for monolithic 3D integrated circuits