Marie et al., 2002 - Google Patents
R, G, B acquisition interface with line-locked clock generator for flat panel displayMarie et al., 2002
View PDF- Document ID
- 4193917190705679226
- Author
- Marie H
- Belin P
- Publication year
- Publication venue
- IEEE Journal of Solid-State Circuits
External Links
Snippet
This paper presents the analysis, design, and experimental results of a triple 8-bit, 80 Msamples/s analog-to-digital acquisition channel with gain and clamp controls, together with a sample clock regenerator. While today's liquid crystal display (LCD) driver systems require …
- 238000005070 sampling 0 abstract description 11
Classifications
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating pulses not covered by one of the other main groups in this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
-
- H—ELECTRICITY
- H03—BASIC ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
- H03D2200/0041—Functional aspects of demodulators
- H03D2200/0049—Analog multiplication for detection
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Dudek et al. | A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line | |
Dehng et al. | Clock-deskew buffer using a SAR-controlled delay-locked loop | |
US6853225B2 (en) | Delay locked loop circuit with duty cycle correction function | |
US7528640B2 (en) | Digital pulse-width control apparatus | |
TW480825B (en) | Low jitter phase-locked loop with duty-cycle control | |
US5644261A (en) | Adjustable precise delay circuit | |
CN102522994B (en) | Clock generation circuit used in analog-to-digital converter (ADC) with high speed and high precision | |
TW201337828A (en) | Integrated multi-channel analog front-end equipment and digital converter for high-speed imaging applications | |
CN1578153A (en) | System capable of adjusting clock phase of ad converter | |
Chuang et al. | A 0.5–5-GHz wide-range multiphase DLL with a calibrated charge pump | |
US20090051347A1 (en) | High frequency delay circuit and test apparatus | |
Marie et al. | R, G, B acquisition interface with line-locked clock generator for flat panel display | |
JPH08330950A (en) | Clock reproducing circuit | |
US6608875B1 (en) | Free-running-frequency adjustment circuit for a clock recovery system | |
Rothermal et al. | Analog phase measuring circuit for digital CMOS ICs | |
JPS58174861A (en) | Property measuring apparatus for analog/digital converter | |
Payne et al. | A 150-MHz translinear phase-locked loop | |
US20020095628A1 (en) | Apparatus and method for reducing skew of a high speed signal | |
Song et al. | A 24-Gb/s MIPI C-/D-PHY receiver bridge chip with phase error calibration supporting FPGA-based frame grabber | |
Lee et al. | An on-chip monitoring circuit for signal-integrity analysis of 8-Gb/s chip-to-chip interfaces with source-synchronous clock | |
US20060022119A1 (en) | Focal plane array with on-chip low-voltage differential serial interface | |
US6617934B1 (en) | Phase locked loop circuits, systems, and methods | |
Marie et al. | R, G, B acquisition interface with line locked clock generator, for LCD driver | |
Raptakis et al. | Laboratory jitter removal circuit for single-bit all-digital frequency synthesis | |
JP2001177354A (en) | Rf amplifier with double-slope phase modulator |