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Symons et al. - Google Patents

Using SystemVerilog Interfaces and Structs for RTL Design

Symons et al.

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Document ID
3738434102204750317
Author
Symons T
Shah N

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Snippet

System verilog interfaces and structs have many useful benefits in RTL design, but they have not been readily adopted due to limited support by the EDA vendors. We used SystemVerilog interfaces and structs in our recent project, and we have recently taped out a …
Continue reading at dvcon-proceedings.org (PDF) (other versions)

Classifications

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    • G06F17/5045—Circuit design
    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
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    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
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