[go: up one dir, main page]

Chen et al., 2010 - Google Patents

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis

Chen et al., 2010

View PDF
Document ID
3495209152629148130
Author
Chen Y
Niu D
Xie Y
Chakrabarty K
Publication year
Publication venue
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

External Links

Snippet

Three-dimensional (3D) ICs promise to overcome barriers in interconnect scaling by leveraging fast, dense inter-die vias, thereby offering benefits of improved performance, higher memory bandwidth, smaller form factors, and heterogeneous integration. However …
Continue reading at scholar.archive.org (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequence
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31717—Interconnect testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
Chen et al. Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Ye et al. TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation
Chi et al. 3D-IC interconnect test, diagnosis, and repair
Chakrabarty et al. TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test
US6423558B1 (en) Method for fabricating integrated circuit (IC) dies with multi-layered interconnect structures
Noia et al. Identification of defective TSVs in pre-bond testing of 3D ICs
US8797056B2 (en) System and method for electronic testing of partially processed devices
Sung et al. A delay test architecture for TSV with resistive open defects in 3-D stacked memories
Spinner et al. Automatic test pattern generation for interconnect open defects
Wang et al. Pre-bond testing of the silicon interposer in 2.5 D ICs
Huang et al. Delay testing and characterization of post-bond interposer wires in 2.5-D ICs
US8312407B2 (en) Integration of open space/dummy metal at CAD for physical debug of new silicon
Lee et al. Grouping-based TSV test architecture for resistive open and bridge defects in 3-D-ICs
Noia et al. Testing and design-for-testability techniques for 3D integrated circuits
Milojevic et al. Design issues in heterogeneous 3D/2.5 D integration
Maity et al. Identification of random/clustered TSV defects in 3D IC during pre-bond testing
Rodríguez-Montañés et al. Postbond test of through-silicon vias with resistive open defects
Chaudhuri et al. Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs
Pasca et al. Configurable thru-silicon-via interconnect built-in self-test and diagnosis
Wang et al. Prebond testing and test-path design for the silicon interposer in 2.5-D ICs
Chen et al. A Scan-Chain Based Built-In Self-Test for ILV in Monolithic 3D ICs
Gulbins et al. Developing digital test sequences for through-silicon vias within 3D structures
Huang et al. Parametric fault testing and performance characterization of post-bond interposer wires in 2.5-D ICs
Roy et al. Faulty tsvs identification and recovery in 3d stacked ics during pre-bond testing
Panth et al. Probe-pad placement for prebond test of 3-D ICs