[go: up one dir, main page]

Aksu et al. - Google Patents

Electrochemical Mechanical Planarization (eCMP) of Copper Overburden

Aksu et al.

View PDF
Document ID
2989119790876493101
Author
Aksu S
Emesh I
Başol B

External Links

Snippet

Abstract A novel Electrochemical Mechanical Planarization (eCMP) process was developed and integrated on the copper plating platform to meet the stringent technical requirements including higher planarization efficiency, higher throughput at lower down force and lower …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—BASIC ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Similar Documents

Publication Publication Date Title
US7183212B2 (en) Polishing method, metallization fabrication method, method for manufacturing semiconductor device and semiconductor device
US6750128B2 (en) Methods of polishing, interconnect-fabrication, and producing semiconductor devices
US6299741B1 (en) Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus
JP4095731B2 (en) Semiconductor device manufacturing method and semiconductor device
US6974525B2 (en) Method and apparatus for electrochemical planarization of a workpiece
US6217416B1 (en) Chemical mechanical polishing slurry useful for copper/tantalum substrates
US6946397B2 (en) Chemical mechanical polishing process with reduced defects in a copper process
US20060219663A1 (en) Metal CMP process on one or more polishing stations using slurries with oxidizers
US20020115283A1 (en) Planarization by selective electro-dissolution
US20060118425A1 (en) Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate
US20030164471A1 (en) Compositions for chemical mechanical planarization of copper
WO2006102539A2 (en) Method and system for electroprocessing conductive layers
US7361582B2 (en) Method of forming a damascene structure with integrated planar dielectric layers
JP2001127019A (en) Polishing fluid for metal and method for polishing substrate using the same
Aksu et al. Electrochemical Mechanical Planarization (eCMP) of Copper Overburden
Pan et al. Copper CMP integration and time dependent pattern effect
Aksu et al. Electrochemical Mechanical Planarization (eCMP) of Copper Thin Films
JP3440826B2 (en) Semiconductor device and method for polishing semiconductor substrate
KR20030070191A (en) Chemical Mechanical Polishing Slurry Composition Having Improved Stability and Polishing Speed on Tantalum Metal Layer
Pan et al. Copper CMP and Process Control
US20070111523A1 (en) Process for conditioning conductive surfaces after electropolishing
Mukherjee et al. Planarization of copper damascene interconnects by spin-etch process: a chemical approach
Surisetty Development and performance analysis of several new CMP slurries for sub-30nm copper technologies
Oh et al. The Effect of Applied Potential and Ph on Electrochemical Polishing of Copper Interconnections
WO2001081043A1 (en) Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate and layer structure made thereby