[go: up one dir, main page]

Czarnecki et al., 2003 - Google Patents

An iterative improvement co-synthesis algorithm for optimization of SOPC architecture with dynamically reconfigurable FPGAs

Czarnecki et al., 2003

Document ID
2885637655925690548
Author
Czarnecki R
Deniziak S
Sapiecha K
Publication year
Publication venue
Euromicro Symposium on Digital System Design, 2003. Proceedings.

External Links

Snippet

In this work, a HW/SW iterative improvement co-synthesis algorithm, which allows for optimization of heterogeneous system architecture with dynamically reconfigurable FPGAs is presented. The algorithm maximizes speed of the system taking into consideration cost …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored programme computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Shine et al. Low-power scheduling with resources operating at multiple voltages
US7657861B2 (en) Method and device for processing data
US6086628A (en) Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
Chatha et al. Hardware-software codesign for dynamically reconfigurable architectures
Shang et al. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs
Wassi et al. Multi-shape tasks scheduling for online multitasking on FPGAs
Chatha et al. An iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling
Nguyen et al. Quantifying the benefits of dynamic partial reconfiguration for embedded vision applications
Marconi Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays
Qu et al. A parallel configuration model for reducing the run-time reconfiguration overhead
Czarnecki et al. An iterative improvement co-synthesis algorithm for optimization of SOPC architecture with dynamically reconfigurable FPGAs
Agarwal et al. Economical duplication based task scheduling for heterogeneous and homogeneous computing systems
Bondalapati et al. Loop pipelining and optimization for run time reconfiguration
Jiashu et al. A design flow for partially reconfigurable heterogeneous multi-processor platforms
Phanibhushana et al. Network-on-chip design for heterogeneous multiprocessor system-on-chip
Edwards et al. The implementation of synchronous dataflow graphs using reconfigurable hardware
Azari et al. Improving performance through path-based hardware/software partitioning
Choudhary et al. FPGA-based adaptive task scheduler for real time embedded systems
Fan et al. A survey on task scheduling method in heterogeneous computing system
Hsiung et al. Exploiting hardware and software low power techniques for energy efficient co-scheduling in dynamically reconfigurable systems
Yang et al. Mapping and frequency joint optimization for energy efficient execution of multiple applications on multicore systems
Liu et al. A graph theoretic optimal algorithm for schedule compression in time-multiplexed FPGA partitioning
Guha et al. Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system
Hsiung et al. Energy efficient co-scheduling in dynamically reconfigurable systems
Czarnecki et al. Resource Constrained Co-synthesis of Self-reconfigurable SOPCs