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Shrivastava et al., 2011 - Google Patents

ESD robust DeMOS devices in advanced CMOS technologies

Shrivastava et al., 2011

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Document ID
2814455494336698069
Author
Shrivastava M
Russ C
Gossner H
Bychikhin S
Pogany D
Gornik E
Publication year
Publication venue
EOS/ESD Symposium Proceedings

External Links

Snippet

Improvement of~ 5X in the I T2 (3.3 mA/μm) of a grounded gate N-DeMOS device compared to a standard design is achieved by simple layout variations with a minor impact on its footprint. Robustness of P-DeMOS devices is shown to be further increased by additional p …
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