[go: up one dir, main page]

Bhaskar et al., 2015 - Google Patents

A survey on implementation of random number generator in FPGA

Bhaskar et al., 2015

View PDF
Document ID
2601564993198807366
Author
Bhaskar P
Gawande P
Publication year
Publication venue
International Journal of Science and Research (IJSR)

External Links

Snippet

A pseudo random number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of random numbers. This paper presents an implementation of pseudo random number generator. The design has …
Continue reading at www.academia.edu (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/588Random number generators, i.e. based on natural stochastic processes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/58Indexing scheme relating to groups G06F7/58 - G06F7/588
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
    • H04L9/06Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H04L9/0668Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator producing a non-linear pseudorandom sequence
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219Countermeasures against side channel or fault attacks

Similar Documents

Publication Publication Date Title
Panda et al. FPGA implementation of 8, 16 and 32 bit LFSR with maximum length feedback polynomial using VHDL
Schellekens et al. FPGA vendor agnostic true random number generator
Datta et al. Design and implementation of multibit LFSR on FPGA to generate pseudorandom sequence number
Güler et al. A high speed, fully digital IC random number generator
Tuncer et al. Random number generation with LFSR based stream cipher algorithms
Dabal et al. FPGA implementation of chaotic pseudo-random bit generators
Durga et al. Design and synthesis of lfsr based random number generator
Panda et al. Design of Multi Bit LFSR PNRG and Performance comparison on FPGA using VHDL
Sewak et al. FPGA implementation of 16 bit BBS and LFSR PN sequence generator: A comparative study
Hathwalia et al. Design and analysis of a 32 bit linear feedback shift register using vhdl
Gupta et al. Efficient hardware implementation of pseudo-random bit generator using dual-CLCG method
Gupta et al. Hardware efficient pseudo-random number generator using chen chaotic system on FPGA
Bhaskar et al. A survey on implementation of random number generator in FPGA
Sadr et al. Physical unclonable function (PUF) based random number generator
Babitha et al. FPGA based N-bit LFSR to generate random sequence number
Gupta et al. Design of modified dual-CLCG algorithm for pseudo-random bit generator
Amsaad et al. A novel security technique to generate truly random and highly reliable reconfigurable ROPUF-based cryptographic keys
Tsoi et al. High performance physical random number generator
Kadam et al. Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator
Petrie et al. A noise-based random bit generator IC for applications in cryptography
Gupta et al. Recent development of hardware-based random number generators on fpga for cryptography
Hussain et al. Design of Secured Lightweight PRNG Circuit using LFSR for Portable IoT Devices
Erkek et al. The implementation of asg and sg random number generators
Kumar et al. Design of energy efficient true random number generator using mux-metastable approach
Gupta et al. Hardware efficient hybrid pseudo-random bit generator using coupled-LCG and multistage LFSR with clock gating network