Boéchat et al., 2013 - Google Patents
An architecture for solving quadratic programs with the fast gradient method on a field programmable gate arrayBoéchat et al., 2013
- Document ID
- 2485007863712348301
- Author
- Boéchat M
- Liu J
- Peyrl H
- Zanarini A
- Besselmann T
- Publication year
- Publication venue
- 21st Mediterranean Conference on Control and Automation
External Links
Snippet
In this paper an architecture for the implementation of gradient-based optimisation methods on a Field Programmable Gate Array (FPGA) is proposed. Combining the algorithmic advantages of gradient-based algorithms with the computational strengths of a tailored …
- 241001442055 Vipera berus 0 description 18
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
- G06F17/13—Differential equations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/11—Complex mathematical operations for solving equations, e.g. nonlinear equations, general mathematical optimization problems
- G06F17/12—Simultaneous equations, e.g. systems of linear equations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Yang et al. | Performance optimization using partitioned SpMV on GPUs and multicore CPUs | |
Gill et al. | A primal-dual augmented Lagrangian | |
Geng et al. | A two-level parallel decomposition approach for transient stability constrained optimal power flow | |
Ferreau et al. | A parallel active-set strategy to solve sparse parametric quadratic programs arising in MPC | |
Boéchat et al. | An architecture for solving quadratic programs with the fast gradient method on a field programmable gate array | |
Jin et al. | Parallel implementation of power system dynamic simulation | |
Mondigo et al. | Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs | |
Wang et al. | Implementation of continuous control set model predictive control method for PMSM on FPGA | |
Rico-Garcia et al. | Comparison of high performance parallel implementations of tlbo and jaya optimization methods on manycore gpu | |
Wang et al. | RSQP: Problem-specific architectural customization for accelerated convex quadratic optimization | |
Cole et al. | Exploiting gpu/simd architectures for solving linear-quadratic mpc problems | |
Doroshenko et al. | Automated Software Design for FPGAs on an Example of Developing a Genetic Algorithm. | |
Conceição et al. | Efficient emulation of quantum circuits on classical hardware | |
Santos et al. | Artificial neural network acceleration on FPGA using custom instruction | |
Mohammed et al. | Towards the reproduction of selected dynamic loop scheduling experiments using SimGrid-SimDag | |
Kumar et al. | Efficient design and implementation of matrix multiplication | |
Jimale et al. | Square matrix multiplication using CUDA on GP-GU | |
Wang et al. | An efficient architecture for floating-point eigenvalue decomposition | |
Tang et al. | Mass expression evaluation parallel algorithm based on ‘expression forest’and its application in power system calculation | |
Lukarski et al. | Hybrid multi-elimination ILU preconditioners on GPUs | |
Kamiabad | Implementing a preconditioned iterative linear solver using massively parallel graphics processing units | |
Wang et al. | Multi-Issue Butterfly Architecture for Sparse Convex Quadratic Programming | |
CN111061675A (en) | Hardware implementation method of system transfer function identification algorithm, computer equipment and readable storage medium for running method | |
Hirai | An application of temporal linear logic to Timed Petri Nets | |
Baharani et al. | High-level design space exploration of locally linear neuro-fuzzy models for embedded systems |