[go: up one dir, main page]

Fedi et al., 2002 - Google Patents

Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits

Fedi et al., 2002

View PDF
Document ID
2398270051355875586
Author
Fedi G
Manetti S
Piccirilli M
Starzyk J
Publication year
Publication venue
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

External Links

Snippet

A procedure for the determination of an optimum set of testable components in the fault diagnosis of analog linear circuits is presented. The proposed method has its theoretical foundation in the testability concept and in the canonical ambiguity group concept. New …
Continue reading at www.researchgate.net (PDF) (other versions)

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3183Generation of test inputs, e.g. test vectors, patterns or sequence
    • G01R31/318342Generation of test inputs, e.g. test vectors, patterns or sequence by preliminary fault modelling, e.g. analysis, simulation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuit
    • G01R31/31903Tester hardware, i.e. output processing circuit tester configuration
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/31718Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836Fault-finding or characterising
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30Marginal testing, e.g. varying supply voltage
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/02Testing of electric apparatus, lines or components, for short-circuits, discontinuities, leakage of current, or incorrect line connection
    • G01R31/024Arrangements for indicating continuity or short-circuits in electric apparatus or lines, leakage or ground faults
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • G06F17/5036Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00Testing or calibrating of apparatus covered by the preceding groups

Similar Documents

Publication Publication Date Title
Fedi et al. Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits
Milor A tutorial introduction to research on analog and mixed-signal circuit testing
Slamani et al. Analog circuit fault diagnosis based on sensitivity computation and functional testing
US7385410B2 (en) Method of and apparatus for testing for integrated circuit contact defects
TWI395959B (en) Method and apparatus for determining relevance values for a detection of a fault on a chip and for determining a fault probability of a location on a chip
Fedi et al. On the application of symbolic techniques to the multiple fault location in low testability analog circuits
Manetti et al. A singular-value decomposition approach for ambiguity group determination in analog circuits
EP0992806A2 (en) Method and apparatus for canceling errors induced by the measurement system during circuit test
Cherubal et al. Parametric fault diagnosis for analog systems using functional mapping
JP3492254B2 (en) Method and apparatus for selecting target components in a limited access test
Ho et al. Hierarchical fault diagnosis of analog integrated circuits
Wey et al. On the implementation of an analog ATPG: The linear case
Ramadoss et al. Test generation for mixed-signal devices using signal flow graphs
CA2050501C (en) Circuit test method
Soma Automatic test generation algorithms for analogue circuits
McDermid Limited access testing: IEEE 1149.4-instrumentation and methods
Abderrahman et al. Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
Burdiek Generation of optimum test stimuli for nonlinear analog circuits using nonlinear programming and time-domain sensitivities
Tadeusiewicz et al. A fault verification method for testing of analogue electronic circuits
Grasso et al. Symbolic techniques in neural network based fault diagnosis of analog circuits
EP0994360B1 (en) Method and apparatus for selecting test point nodes for limited access circuit test
Worsman et al. Enhancing the fault diagnosis of linear analog circuit steady-state DC testing through the analysis of equivalent faults
Fedi et al. A symbolic approach for testability evaluation in fault diagnosis of nonlinear analog circuits
EP0992804B1 (en) Method and apparatus for selecting stimulus locations during limited access circuit test
Bhattacharya et al. Optimized wafer-probe and assembled package test design for analog circuits