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Lubaszewski et al., 1992 - Google Patents

On the design of self-checking boundary scannable boards

Lubaszewski et al., 1992

Document ID
2005707310809126857
Author
Lubaszewski M
Courtois B
Publication year
Publication venue
Proceedings International Test Conference 1992

External Links

Snippet

In this paper the Boundary Scan technique and the Un@ ed Built-In Self-Test scheme are combined in order to propose a strategy suitable for the manufacturing, the field testing and the concurrent error detection on integrated circuits and board interconnects. Such …
Continue reading at www.computer.org (other versions)

Classifications

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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
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    • G01R31/318558—Addressing or selecting of subparts of the device under test
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    • G01R31/318541—Scan latches or cell details
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    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
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    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

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