[go: up one dir, main page]

Miyamoto et al., 2003 - Google Patents

A fine-grained programmable logic module with small amount of configuration data for dynamically reconfigurable field-programmable gate array

Miyamoto et al., 2003

Document ID
1929528453799668649
Author
Miyamoto N
Karnan L
Kotani K
Ohmi T
Publication year
Publication venue
Japanese Journal of Applied Physics

External Links

Snippet

Dynamically customizable and reconfigurable hardware architecture for a specific task on demand is one of the most important issues to bring out a novel-computing paradigm in the era of system LSIs. Our target is to realize a flexible processor which is a kind of dynamically …
Continue reading at iopscience.iop.org (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—BASIC ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

Similar Documents

Publication Publication Date Title
Marshall et al. A reconfigurable arithmetic array for multimedia applications
Kocan et al. Logic modules with shared SRAM tables for field-programmable gate arrays
Miller et al. Multiple valued logic: Concepts and representations
Tung et al. A low-power high-speed hybrid CMOS full adder for embedded system
JP3253347B2 (en) Functionally complete logic circuits with self-timing
Gavrilov et al. Library-less synthesis for static CMOS combinational logic circuits
JP3248927B2 (en) Arithmetic logic operation unit and operation function execution method
Gordon-Ross et al. A one-cycle FIFO buffer for memory management units in manycore systems
Miyamoto et al. A fine-grained programmable logic module with small amount of configuration data for dynamically reconfigurable field-programmable gate array
Hsiao et al. High‐performance Multiplexer‐based Logic Synthesis Using Pass‐transistor Logic
CN116388748A (en) Self-gated flip-flop for dynamic power reduction
Zimmermann et al. Low-power logic styles: CMOS vs CPL
WO1986007173A1 (en) Cmos full adder cell e.g. for multiplier array
Riente et al. Exploring the 3-D integrability of perpendicular nanomagnet logic technology
Supritha et al. High speed and efficient ALU using modified booth multiplier
Flak et al. Dense CMOS implementation of a binary‐programmable cellular neural network
JP2007226944A (en) Semiconductor memory and semiconductor integrated circuit
Sakaidani et al. Flexible processor based on full-adder/D-flip-flop merged module (FDMM)
Hussain et al. Exploring FPGA Logic Block Architecture for Reduced Configuration Memory.
York et al. Design and VLSI implementation of mod-127 multiplier using cellular automaton-based data compression techniques
Palchaudhuri et al. High performance bit-sliced pipelined comparator tree for FPGAs
Rahman et al. Six-correction logic (SCL) gates in quantum-dot cellular automata (QCA)
Komatsu et al. Architecture of an asynchronous FPGA for handshake-component-based design
Mora et al. Partial product reduction based on look-up tables
Bai et al. A multiple-valued reconfigurable VLSI architecture using binary-controlled differential-pair circuits