[go: up one dir, main page]

Laffely et al., 2003 - Google Patents

Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores

Laffely et al., 2003

View PDF
Document ID
18372490551363327630
Author
Laffely A
Liang J
Tesseir R
Burleson W
Publication year
Publication venue
Proceedings 2003 International Conference on Image Processing (Cat. No. 03CH37429)

External Links

Snippet

For motion estimation (ME) and discrete cosine transform (DCT) of MPEG video encoding, content variation and perceptual tolerance in video signals can be exploited to gracefully trade quality for low power. As a result, power-aware hardware cores have been proposed …
Continue reading at www.ecs.umass.edu (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234—Action, measure or step performed to reduce power consumption
    • G06F1/3287—Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored programme computers
    • G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16—Constructional details or arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10—Energy efficient computing
    • Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1278—Power management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10—Energy efficient computing
    • Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1207—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply acting upon the main processing unit
    • Y02B60/1217—Frequency modification
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—INDEXING SCHEME RELATING TO CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. INCLUDING HOUSING AND APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B60/00—Information and communication technologies [ICT] aiming at the reduction of own energy use
    • Y02B60/10—Energy efficient computing
    • Y02B60/12—Reducing energy-consumption at the single machine level, e.g. processors, personal computers, peripherals, power supply
    • Y02B60/1232—Acting upon peripherals
    • Y02B60/1235—Acting upon peripherals the peripheral being a bus

Similar Documents

Publication Publication Date Title
Abnous et al. Ultra-low-power domain-specific multimedia processors
Niyogi et al. Speed and voltage selection for GALS systems based on voltage/frequency islands
US7222244B2 (en) Semiconductor device including a prediction circuit to control a power status control circuit which controls the power status of a function circuit
EP2163097A2 (en) Adaptive video encoding apparatus and methods
US20020059481A1 (en) Method and apparatus for a multimedia application specific processor
US7570651B2 (en) High-performance reconfigurable interconnect for concurrent operation of multiple systems
Lehtoranta et al. A parallel MPEG-4 encoder for FPGA based multiprocessor SoC
BV Silicon System Design of Media and Communications Applications
Laffely et al. Adaptive systems on a chip (aSoC) for low-power signal processing
Laffely et al. Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores
Kim et al. Hardware‐Software Implementation of MPEG‐4 Video Codec
Chang et al. Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network
US8526503B2 (en) OCN-based moving picture decoder
Hilgenstock et al. A video signal processor for MIMD multiprocessing
Lahtinen et al. Interconnection scheme for continuous-media systems-on-a-chip
Saponara et al. Homogeneous and Heterogeneous MPSoC Architectures with Network‐On‐Chip Connectivity for Low‐Power and Real‐Time Multimedia Signal Processing
Lucas et al. Application development with the FlexWAFE real-time stream processing architecture for FPGAs
Reddy et al. New VLSI architecture for motion estimation algorithm
Bolcioni et al. A low-power, voice-controlled, H. 263 video decoder for portable applications
Nguyen et al. An Efficient Implementation of H. 264/AVC Integer Motion Estimation Algorithm on Coarse-grained Reconfigurable Computing System.
Pirsch et al. Very large scale integration (VLSI) architectures for video signal processing
Laffely An interconnect-centric approach for adapting voltage and frequency in heterogeneous system-on-a-chip
Xu et al. Design a Low-Power H. 264/AVC Baseline Decoder at All Abstraction Levels—A Showcase
Kawakami et al. A 50% power reduction in H. 264/AVC HDTV video decoder LSI by dynamic voltage scaling in elastic pipeline
Papanikolaou et al. Architectural and physical design optimizations for efficient intra-tile communication