[go: up one dir, main page]

Amarú et al., 2015 - Google Patents

The EPFL combinational benchmark suite

Amarú et al., 2015

View PDF
Document ID
17564789240662658364
Author
Amarú L
Gaillardon P
De Micheli G
Publication year
Publication venue
Hypotenuse

External Links

Snippet

In this paper, we present the EPFL combinational benchmark suite. We aim at completing existing benchmark suites by focusing only on natively combinational benchmarks. The EPFL ccombinational benchmark suite consists of 23 combinational circuits designed to …
Continue reading at si2.epfl.ch (PDF) (other versions)

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5009—Computer-aided design using simulation
    • G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5045—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30286—Information retrieval; Database structures therefor; File system structures therefor in structured data stores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50—Computer-aided design
    • G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
    • G06F17/5081—Layout analysis, e.g. layout verification, design rule check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
    • G06F17/30861—Retrieval from the Internet, e.g. browsers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00—Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78—Power analysis and optimization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for programme control, e.g. control unit
    • G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Similar Documents

Publication Publication Date Title
Amarú et al. The EPFL combinational benchmark suite
Ho et al. Efficient floating point precision tuning for approximate computing
Mazahir et al. Probabilistic error modeling for approximate adders
Kouretas et al. Low-power logarithmic number system addition/subtraction and their impact on digital filters
Sekanina et al. Automated search-based functional approximation for digital circuits
Palem Inexactness and a future of computing
Karandikar et al. CDPU: Co-designing compression and decompression processing units for hyperscale systems
Barrois et al. The hidden cost of functional approximation against careful data sizing—A case study
Vasicek et al. Evolutionary design of complex approximate combinational circuits
Garg et al. Bit-width-aware constant-delay run-time accuracy programmable adder for error-resilient applications
Vaeztourshizi et al. EGAN: A framework for exploring the accuracy vs. energy efficiency trade-off in hardware implementation of error resilient applications
Jovanovic et al. Binary division power models for high-level power estimation of FPGA-based DSP circuits
Češka et al. ADAC: Automated design of approximate circuits
Damaj et al. Optimizing FPGA implementation of high-precision chaotic systems for improved performance
De Micheli The EPFL combinational benchmark suite
Fiore Efficient approximate wordlength optimization
Ren et al. An energy-based discontinuous Galerkin method for the nonlinear Schrödinger equation with wave operator
Vera et al. A dynamic dual fixed‐point arithmetic architecture for FPGAs
Menard et al. High‐Level Synthesis under Fixed‐Point Accuracy Constraint
Amarú et al. Multi-level logic benchmarks: An exactness study
Lee et al. Hardware‐Efficient Quantized Stochastic Computing With Reduced Precision Stochastic Number Generator and LFSR‐Based Counter
Prasad et al. Performance Analysis of Low Power Inexact Recursive Multipliers for Image Processing Applications
Alexander et al. An improved algorithm for assessing the overall quantisation error in FPGA based CORDIC systems computing a vector magnitude
Wang et al. Core‐Level Modeling and Frequency Prediction for DSP Applications on FPGAs
Shi et al. Imprecise datapath design: An overclocking approach