Madhavan et al., 2021 - Google Patents
Physical Design and Implementation of Lakshya-Sub-system of Built in Self Test SystemMadhavan et al., 2021
- Document ID
- 17487010212826435595
- Author
- Madhavan S
- Phadke R
- et al.
- Publication year
- Publication venue
- 2021 International Conference on Circuits, Controls and Communications (CCUBE)
External Links
Snippet
The Integrated Circuits (IC) designed today are complex and hence require a good Physical Design strategies and optimization. Physical Design process involves placing all components including standard cell and macros inside the core area of the integrated …
- 230000015654 memory 0 abstract description 23
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5072—Floorplanning, e.g. partitioning, placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5077—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
- G06F17/5031—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/12—Design for manufacturability
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/20—Handling natural language data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/84—Timing analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/62—Clock network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/08—Multi-objective optimization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Panth et al. | Shrunk-2-D: A physical design methodology to build commercial-quality monolithic 3-D ICs | |
| Donno et al. | Clock-tree power optimization based on RTL clock-gating | |
| US9141740B2 (en) | Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data | |
| CN107918694B (en) | Method for reducing delay on an integrated circuit | |
| CN107066681B (en) | Integrated circuits and computer-implemented methods of fabricating integrated circuits | |
| US20160085898A1 (en) | Automated layout for integrated circuits with nonstandard cells | |
| US7013438B1 (en) | System chip synthesis | |
| US10831973B2 (en) | Semiconductor process modeling to enable skip via in place and route flow | |
| KR100741915B1 (en) | Design Method of Semiconductor Device to Efficiently Reflect the Time Delay Effect on Dummy Metal Filling | |
| Xu et al. | Enhanced 3D implementation of an Arm® Cortex®-A microprocessor | |
| US10223485B2 (en) | Reliability verification based on combining voltage propagation with simulation | |
| Madhavan et al. | Physical Design and Implementation of Lakshya-Sub-system of Built in Self Test System | |
| Shenoy et al. | Design implementation of synchronous fifo-synthesis, pnr, sta and physical verification | |
| KR20170094744A (en) | Integrated circuit and computer-implemented method for manufacturing the same | |
| US10204180B1 (en) | Method, system, and computer program product for implementing electronic designs with automatically generated power intent | |
| US20180052951A1 (en) | Acceleration Of Voltage Propagation Based On Device Chain Reduction | |
| US20110185335A1 (en) | Determining an order for visiting circuit blocks in a circuit design for fixing design requirement violations | |
| US20040003363A1 (en) | Integrated circuit design and manufacture utilizing layers having a predetermined layout | |
| Jenila et al. | Implementation of routing-denser PnR flow for an efficient IC block Level design | |
| US12045553B2 (en) | Method for implementing an integrated circuit comprising a random-access memory-in-logic | |
| Friedrich et al. | Design methodology for the IBM POWER7 microprocessor | |
| CN120706360B (en) | A Method for Designing a Full-Process Script for Digital Backend | |
| Bharath et al. | HBM3 Architectural Specific Checks and Timing Closure | |
| Melikyan | Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells | |
| US20260017442A1 (en) | Integrated circuit layout and method of generating thereof |