Sohofi et al., 2015 - Google Patents
System‐level assertions: approach for electronic system‐level verificationSohofi et al., 2015
View PDF- Document ID
- 16803062779515763204
- Author
- Sohofi H
- Navabi Z
- Publication year
- Publication venue
- IET Computers & Digital Techniques
External Links
Snippet
As design of digital systems become more complex and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Now that design at the register transfer level (RTL) has reached its maturity, the focus is shifting to …
- 238000000034 method 0 abstract description 32
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5022—Logic simulation, e.g. for logic circuit operation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/504—Formal methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5068—Physical circuit design, e.g. layout for integrated circuits or printed circuit boards
- G06F17/5081—Layout analysis, e.g. layout verification, design rule check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5009—Computer-aided design using simulation
- G06F17/5036—Computer-aided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/505—Logic synthesis, e.g. technology mapping, optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/30—Information retrieval; Database structures therefor; File system structures therefor
- G06F17/30861—Retrieval from the Internet, e.g. browsers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/70—Fault tolerant, i.e. transient fault suppression
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/78—Power analysis and optimization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2217/00—Indexing scheme relating to computer aided design [CAD]
- G06F2217/86—Hardware-Software co-design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/20—Handling natural language data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Apvrille et al. | A UML-based environment for system design space exploration | |
Sohofi et al. | Assertion-based verification for system-level designs | |
US11347917B2 (en) | Determining and verifying metastability in clock domain crossings | |
Pierre et al. | A tractable and fast method for monitoring SystemC TLM specifications | |
Letychevskyi et al. | Modeling method for development of digital system algorithms based on programmable logic devices | |
CN118052196A (en) | Chip verification test method and device based on UVM and electronic equipment | |
Jiang et al. | PyH2: Using PyMTL3 to create productive and open-source hardware testing methodologies | |
Ebeid et al. | HDL code generation from UML/MARTE sequence diagrams for verification and synthesis | |
Piscitelli et al. | A Signature‐Based Power Model for MPSoC on FPGA | |
Bombieri et al. | Reusing RTL assertion checkers for verification of SystemC TLM models | |
Sohofi et al. | System‐level assertions: approach for electronic system‐level verification | |
Suhaib et al. | Validating families of latency insensitive protocols | |
Ahuja et al. | Low Power Design with High-Level Power Estimation and Power-Aware Synthesis | |
Brinkmann et al. | Formal verification—the industrial perspective | |
Borrione et al. | Property-based dynamic verification and test | |
Lantreibecq et al. | Model checking and co-simulation of a dynamic task dispatcher circuit using CADP | |
Kebaili et al. | Enabler-based synchronizer model for clock domain crossing static verification | |
Baguma | High level synthesis of fpga-based digital filters | |
US12340157B2 (en) | Non-functional loopback-paths removal from IO-pads using logic replication | |
Jenihhin et al. | PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams | |
Sinha | Automated techniques for formal verification of SoCs | |
Mohamed | Towards a ML-Assisted EDA Tools | |
Golshan | Design Verification | |
Braga et al. | The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems | |
Jenihhin et al. | PSL assertion checking with temporally extended high-level decision diagrams |