Zeng et al., 1996 - Google Patents
Wormhole routing and its chip designZeng et al., 1996
- Document ID
- 14862158537258061352
- Author
- Zeng R
- Dong X
- Zhu M
- Publication year
- Publication venue
- Proceedings Second International Symposium on Parallel Architectures, Algorithms, and Networks (I-SPAN'96)
External Links
Snippet
Wormhole routing is a key technique in the design of Dawning 1000 which is the first MPP system made in China. In this paper, wormhole routing is introduced, and an algorithm based on wormhole routing, a chip architecture and its logic design are also described …
- 238000000034 method 0 abstract description 3
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/25—Routing or path finding through a switch fabric
- H04L49/253—Connections establishment or release between ports
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Plana et al. | A GALS infrastructure for a massively parallel multiprocessor | |
KR900006793B1 (en) | Packet switched multiple queue nxm switch mode and processing method | |
Dall'Osso et al. | Xpipes: a latency insensitive parameterized network-on-chip architecture for multi-processor SoCs | |
US5559970A (en) | Crossbar switch for multi-processor, multi-memory system for resolving port and bank contention through the use of aligners, routers, and serializers | |
Duato et al. | Interconnection networks | |
Dias et al. | Packet switching interconnection networks for modular systems | |
US10355851B2 (en) | Methods and systems for synchronization between multiple clock domains | |
Duato et al. | Performance evaluation of adaptive routing algorithms for k-ary n-cubes | |
Flaig | VLSI mesh routing systems | |
US8549207B2 (en) | Crossbar circuitry for applying an adaptive priority scheme and method of operation of such crossbar circuitry | |
US8230152B2 (en) | Crossbar circuitry and method of operation of such crossbar circuitry | |
KR20220004216A (en) | Control Flow Barriers and Reconfigurable Data Processors | |
Krylov et al. | Globally asynchronous, locally synchronous clocking and shared interconnect for large-scale SFQ systems | |
US5594866A (en) | Message routing in a multi-processor computer system with alternate edge strobe regeneration | |
Patil et al. | Design and implementation of asynchronous NOC architecture with buffer-less router | |
Ax et al. | Comparing synchronous, mesochronous and asynchronous NoCs for GALS based MPSoCs | |
US5163068A (en) | Arbitrarily large clock networks with constant skew bound | |
Song et al. | Asynchronous spatial division multiplexing router | |
Zeng et al. | Wormhole routing and its chip design | |
Yantchev et al. | Low-latency asynchronous FIFO buffers | |
Hossain et al. | Extended-butterfly fat tree interconnection (EFTI) architecture for network on chip | |
May et al. | Hiper: A compact narrow channel router with hop-by-hop error correction | |
Sakai et al. | Design and implementation of a circular omega network in the EM-4 | |
Siddagangappa et al. | An efficient asynchronous spatial division multiplexing router for network-on-chip on the hardware platform. | |
Nyathi et al. | Multiple clock domain synchronization for network on chip architectures |