Negrini et al., 1986 - Google Patents
Fault tolerance techniques for array structures used in supercomputingNegrini et al., 1986
- Document ID
- 13882845232889691130
- Author
- Negrini R
- Sami M
- Stefanelli R
- Publication year
- Publication venue
- Computer
External Links
Snippet
Two philosophies of parllelism. Since advanced application areas have consistently demanded computing power and speed far greater than that obtainable from technology that incorporates conventional architectures, the only acceptable solution has always been to …
- 238000000034 method 0 title description 25
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a programme unit and a register, e.g. for a simultaneous processing of several programmes
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Error detection; Error correction; Monitoring responding to the occurence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Negrini et al. | Fault tolerance techniques for array structures used in supercomputing | |
US5931959A (en) | Dynamically reconfigurable FPGA apparatus and method for multiprocessing and fault tolerance | |
Mitra et al. | Reconfigurable architecture for autonomous self-repair | |
Koren et al. | Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems | |
Kim et al. | On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement | |
JPH04267466A (en) | Parallel processing system and data comparing method | |
Chen et al. | A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors | |
Jiang et al. | Reconfiguring three-dimensional processor arrays for fault-tolerance: Hardness and heuristic algorithms | |
Fukushi et al. | A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches | |
Fukushima et al. | An improved reconfiguration method for degradable processor arrays using genetic algorithm | |
Singh et al. | A modular fault-tolerant binary tree architecture with short links | |
Fukushi et al. | Reconfiguration algorithm for degradable processor arrays based on row and column rerouting | |
Horita et al. | An efficient method for reconfiguring the 1 1/2 track-switch mesh array | |
Jiang et al. | Reducing the interconnection length for 3D fault-tolerant processor arrays | |
Boubekeur et al. | A full experience of designing a wafer scale 2D array | |
Fukushi et al. | Self-reconfigurable mesh array system on FPGA | |
Saucier et al. | Practical experiences in the design of a wafer scale 2-D array | |
Latifi et al. | Nonplanar VLSI arrays with high fault-tolerance capabilities | |
Jain et al. | A fault-tolerant array processor designed for testability and self-reconfiguration | |
Campbell et al. | Hierarchical fault tolerance for 3D microelectronics | |
Horiguchi | Self-Reconfigurable Mesh Array System on FPGA | |
Butner et al. | A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors | |
Popli et al. | Fault diagnosis and reconfiguration for reliable VLSI arrays | |
Howells et al. | Defect tolerant interconnects for VLSI | |
Kshirsagar et al. | Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems |