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Tsen et al., 2009 - Google Patents

A combined decimal and binary floating-point multiplier

Tsen et al., 2009

Document ID
13623909899063771835
Author
Tsen C
González-Navarro S
Schulte M
Hickmann B
Compton K
Publication year
Publication venue
2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

External Links

Snippet

In this paper, we describe the first hardware design of a combined binary and decimal floating-point multiplier, based on specifications in the IEEE 754-2008 floating-point standard. The multiplier design operates on either (1) 64-bit binary encoded decimal floating …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

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    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding, overflow
    • G06F7/49942—Significance control
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    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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    • G06F7/52—Multiplying; Dividing
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    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
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    • G06F7/50—Adding; Subtracting
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    • G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application

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