Ghosh et al., 1995 - Google Patents
VLSI implementation of an efficient ASIC architecture for real-time rotation of digital imagesGhosh et al., 1995
- Document ID
- 13217514834278317240
- Author
- Ghosh I
- Majumdar B
- Publication year
- Publication venue
- International journal of pattern recognition and artificial intelligence
External Links
Snippet
This paper describes the design and the VLSI implementation of a novel architecture that performs image rotation in real time. In order to improve throughput, we divide an image- frame into a number of windows. The rotation of each window-center as well as the final …
- 238000000034 method 0 abstract description 13
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/78—Architectures of general purpose stored programme computers comprising a single central processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored programme computers
- G06F15/80—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored programme computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F1/00—Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T11/00—2D [Two Dimensional] image generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformation in the plane of the image, e.g. from bit-mapped to bit-mapped creating a different image
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T15/00—3D [Three Dimensional] image rendering
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Maharatna et al. | Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture | |
US5657403A (en) | Vision coprocessing | |
AU747283B2 (en) | Data processing system for logically adjacent data samples such as image data in a machine vision system | |
Tagzout et al. | Hough transform algorithm for FPGA implementation | |
US12141225B2 (en) | Inference accelerator using logarithmic-based arithmetic | |
US20240311626A1 (en) | Asynchronous accumulator using logarithmic-based arithmetic | |
Han et al. | MetaVRain: A mobile neural 3-D rendering processor with bundle-frame-familiarity-based NeRF acceleration and hybrid DNN computing | |
Chen et al. | An FPGA-based RGBD imager | |
Ghosh et al. | VLSI implementation of an efficient ASIC architecture for real-time rotation of digital images | |
Wills et al. | Processing architectures for smart pixel systems | |
Boo et al. | VLSI implementation of an edge detector based on Sobel operator | |
Ghosh et al. | Design of an application specific VLSI chip for image rotation | |
Chen et al. | A parallel reconfigurable architecture for real-time stereo vision | |
Bensaali et al. | An FPGA implementation of 3D affine transformations | |
Ma et al. | Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier | |
Bhandakar et al. | VLSI implementation of real-time image rotation | |
Juskiw et al. | Interactive rendering of volumetric data sets | |
Lu et al. | MorphoSys: a reconfigurable processor targeted to high performance image application | |
Mattson et al. | Generalized image warping using enhanced lookup tables | |
Lindskog | PICAP 3: An SIMD architecture for multi-dimensional signal processing | |
Waidyasooriya et al. | Memory allocation for window-based image processing on multiple memory modules with simple addressing functions | |
Papadopoulos et al. | Parallel processing of digital images using a modular architecture | |
Wong et al. | A new scalable systolic array processor architecture for simultaneous discrete convolution of k different (nxn) filter coefficient planes with a single image plane | |
Benedetti et al. | A novel system architecture for real-time low-level vision | |
Komarek et al. | VLSI architectures for block matching algorithms |